| 1 |
안형근, "Optimizing the Circuit for fmding 2 Error Positions of 2 error Correcting Reed Solomon Decoder," 한국통신학회논문지, pp 8-13 ,2011 January.
|
| 2 |
J.Jiang and K. Narayanan, "Iterative soft decision decoding of Reed Solommon codes based on adaptive paritycheck matrices," in Proc. ISIT, 2004.
|
| 3 |
Think Silicon Ltd, "Galois Field Multiplier Generator Version 1.0", 2008
|
| 4 |
Joschi Brauchle, Ralf Koetter; A Systematic Reed-Solomon Encoder with Arbitrary Parity Positions, IEEE GLOBECOM, 2009 Proceedings.
|
| 5 |
T.K. Moon, Error Correction Coding: Mathematical Methods and Algorithms, Hoboken, NJ: John Wiley & Sons,lnc.,2005.
|
| 6 |
D. Canright, "Avoid Mask Re-use in Galois Multipliers", Applied Math., Naval Postgraduate School, Monterey CA 93943, USA, 26 November 2008
|
| 7 |
안형근, "New Efficient Design of Reed Solomon Encoder Which has Arbitrary Parity Positions Without Galois Field Multiplier", 한국통신학회논문지, pp.984-990, Vol.35, No 6
|
| 8 |
Ming Jang, Bin Nemat, "Implementation of Switch box Using a Subfield", USP7,532,721, 2009
|
| 9 |
Y osef Stein, "Compact Galois Field Multiplier Engine", USP 7,177,891, Feb 13, 2007
|
| 10 |
Pusan Patel, "Parallel Multiplier Designs for the Galois/Counter Mode of Operation", Univ. of Wateroo Canada, Dep. of EECS, 2008 MS Thesis.
|
webmaster
