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http://dx.doi.org/10.9708/jksci.2020.25.02.041

Low-area Bit-parallel Systolic Array for Multiplication and Square over Finite Fields  

Kim, Keewon (Dept. of Applied Computer Engineering, Dankook University)
Publication Information
Journal of the Korea Society of Computer and Information / v.25, no.2, 2020 , pp. 41-48 More about this Journal
Abstract
In this paper, we derive a common computational part in an algorithm that can simultaneously perform multiplication and square over finite fields, and propose a low-area bit-parallel systolic array that reduces hardware through sequential processing. The proposed systolic array has less space and area-time (AT) complexity than the existing related arrays. In detail, the proposed systolic array saves about 48% and 44% of Choi-Lee and Kim-Kim's systolic arrays in terms of area complexity, and about 74% and 44% in AT complexity. Therefore, the proposed systolic array is suitable for VLSI implementation and can be applied as a basic component in hardware constrained environment such as IoT.
Keywords
Finite fields; Multiplication; Square; Systolic array; Cryptography;
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Times Cited By KSCI : 3  (Citation Analysis)
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