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Efficient Operator Design Using Variable Groups  

Kim, Yong-Eun (Div. of Electronic & Information Engineering Chonbuk University)
Chung, Jin-Gyun (Div. of Electronic & Information Engineering Chonbuk University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.1, 2008 , pp. 37-42 More about this Journal
Abstract
In this paper, we propose a partial product addition method using variable groups in the design of operators such as multipliers and digital filters. By this method, full adders can be replaced with simple logic circuits. To show the efficiency of the proposed method, we applied the method to the design of squarers and precomputer blocks of FIR filters. In case of 7 bit and 8 bit squarers, it is shown that by the proposed method, area, power and delay time can be reduced up to {22.1%, 20.1%, 14%} and {24.7%, 24.4%, 6.7%}, respectively, compared with the conventional method. The proposed FIR precomputer circuit leads to up to {63.6%, 34.4%, 9.8%} reduction in area, power consumption and propagation delay compared with previous method.
Keywords
variable group; multiplier; partial product; squarer; FIR precomputer; shift-addition;
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1 K. Hwang, Computer Arithmetic: Principles, Architecture, and Design. New York: Wiley, 1979
2 R. K. Kolagotla , W. R. Griescbach, and H. R. Srinivas, 'VLSI implementation of a 350 MHz 0.35um 8 bit merged squarer,' Electronic Letters, vol. 34, pp. 47-48, Jan. 1998   DOI   ScienceOn
3 K. E. Wires, M. J. Schulte, L. P. Marquette, and P. I. Balzola, 'Combined unsigned and two's complement squarers,' in 33rd Asilomar Conference on Signals, Systems, and Computers, pp. 1215-1219, 1999
4 C. S. Wallace, 'A suggestion for a fast multiplier', IEEE Trans. on Electron. Comp., vol. 13, pp. 14-17, 1964   DOI   ScienceOn
5 L. Dadda, 'Some schemes for parallel multipliers,' Alta Frequenza, vol. 34, pp. 349-356, 1965
6 G. Goto, T. Sato, M. Nakajiama, and T. Sukemura, 'A 54$\times$54 regulary structured tree multiplier,' IEEE J. Solid-State Circuits, vol. 27, pp. 1229-1236, Sept. 1992   DOI   ScienceOn
7 K. A. C. Bickerstaff, M. Schulte, and E. E. Swartzlander, 'Reduced area multipliers,' in Proc. Int. Conf. on Application-Specific Array Processors, PP. 478-489, 1993
8 J. Park, K. Muhammad and K. Roy, 'High performance FIR filter design based on sharing multiplication,' IEEE Transaction on VLSI systems, vol. 11, pp. 244-253. April. 2003   DOI   ScienceOn
9 J. Pihl and E. Aas, 'A multiplier and squarer generator for high performance DSP applications,' in Proc. IEEE 39th Midwest Symp. on Circuit and Systems, 1996, pp. 109-112