• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.638-644
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• 2018

Relay systems have recently gained attentions because of its capability of cell coverage extension and the power gain as the one of key technologies for 5G. Relays can be exploited for small-cell base stations and the autonomous network, where communication devices communicate with each other cooperatively. Therefore, the relay technology is expected to enable the low power and large capacity communication. In order to maximize the benefits of using a limited number of relays, the efficient relay selection method is required. Especially, when two nodes exchange their data with each other via relay, the relay selection can maximize the average data rate by the spatial location of the relay. For this purpose, the average data rate is analyzed first according to the relay selection. In this paper, we analyzed the average data rate when two nodes exchange their data via dual-hop decode and forward relaying considering the interference by the concurrent transmission under Nakagami-m fading channel. The correctness of the analysis is verified by the Monte Carlo simulation. The results show that the concurrent transmission is superior to the non-concurrent transmission in the high required data rate region rather than in the low required data rate region.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.45-51
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• 2003

In this paper, a scan-based low power BIST (Built-In Self-Test) architecture is proposed. The proposed architecture is based on STUMPS, which uses a LFSR (Linear Feedback Shift Register) as the test generator, a MISR(Multiple Input Shift Register) as the reponse compactor, and SRL(Shift Register Latch) channels as multiple scan paths. In the proposed BIST a degenerate MISR structure is used for every SRL channel; this offers reduced area overheads and has less impact on performance than the STUMPS techniques. The proposed BIST is designed to support both test-per-clock and test-per-scan techniques, and in test-per-scan the total power consumption of the circuit can be reduced dramatically by suppressing the effects of scan data on the circuits. Results of the experiments on ISCAS 89 benchmark circuits show that this architecture is also suitable for detecting path delay faults, when the hamming distance of the data in the SRL channel is considered.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.27-33
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• 2011

Recently many display devices support the digital display interface as display market growth. DisplayPort is a next generation display interface at the PC, projector and high definition content applications in more widely used connection solution development. This paper implements multiple streams based on the behavior of the main link that is suitable for the display port v1.1a standard. The limit point of Displayport, interface between the Sink Device and Sink Device is also implemented. And two or more differential image data are enable to output the result through four Lanes stated in display port v1.1a, of two or more display devices without the addition of a separate Lane. The Multiple Video Streaming Controller is implemented with 6,222 ALUTs and 6,686 register, 999,424 of block memory bits synthesized using Quartus II at Altera Audio/Video Development board (Stratix II GX FPGA Chip).

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.9
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• pp.9-16
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• 2007

In the multiuser OFDM systems, an efficient resource allocation is necessary in order to provide the service to more users. This paper proposes u improved subcarrier allocation algorithm, satisfying each user's QoS under the limited resources, to maximize total transmission data rate and spectral efficiency. The proposed algorithm is divided into two steps. In the first step, users who are eligible for services are determined by using BER, user's minimum data rate requirement, and channel information. In the second step, first, subcarriers are allocated to users on the basis of channel state. And then, reallocation is fulfilled so that the total transmission data rate is maximized and the least reduction in the overall throughput is caused.

• Journal of IKEEE
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• v.15 no.2
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• pp.113-121
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• 2011

This paper presents the design of a fast auxiliary channel bus for DisplayPort 1.2 interface. The fast auxiliary channel supports Manchester transactions at 1Mbps and fast auxiliary transactions at 780Mbps. The Manchester transaction is used for managing the main link and auxiliary channel and the fast auxiliary transaction is for data transfer via the auxiliary channel. Simplified serial bus architecture is proposed to be implemented in fast auxiliary channel. The fast auxiliary channel transmitter and receiver are implemented with 7,648 LUTs and 6,020 slice register synthesized in Xilinx Vertex4 FPGA and can be operated at 72MHz to support 720Mbps.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.6
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• pp.1089-1096
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• 2019

Recently, small-scale IoT services using a small amount of information through low-performance computing have been spread. It requires low cost, low-power, and long-distance communication technologies with wide communication radius, relatively low power consumption. This paper proposes a MAC layer and routing protocol that supports multi-hop transmission in small-scale IoT environment distributed over a large area based on LoRa communication and delivering a small amount of sensing data. The terminal node is mobile and the communication type provides bidirectional transmission between the terminal node and the network application server. By applying the proposed protocol, a production line monitoring system for smart factory was implemented. It was confirmed that the basic monitoring functions are normally performed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.24-30
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• 2009

In this paper, the FPGA modem platform complying with 3GPP Release 7 eHSPA specifications and its regularized verification flow are proposed. The FFGA platform consists of modem board supporting physical layer requirements, MCU and DSP core embedded control board to drive the modem board, and peripheral boards for RF interfacing and various equipment interfaces. On the other hand, the proposed verification flow has been regularized into three categories according to the correlation degrees of hardware-software inter-operation, such as simple function test, scenario test call processing and system-level performance test. When it comes to real implementations, the emulation verification strategy for low power mobile SoC is also introduced.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.10
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• pp.191-200
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• 2007

As the IEEE 802.11 WLAN has widely installed as a high-speed wireless network information infrastructure, there has been growing interest in both security and mobility of mobile terminals. However, for the case of mobile terminal employing IEEE 802.11i security standard, it is known that the user authentication procedure of IEEE 802.1x for stronger security enforcement may, due to its large delay, not be suitable for real-time multimedia communication. In this paper, we have proposed fast authentication method to resolve the above authentication delay problem, and verifies its performance via simulation analysis. Mobile terminals can get AP information reliably, and selectively execute authentication in advance during handover, which results in fast user authentication. In addition, by effectively managing the authentication information in mobile terminal, which are distributed in advance for pre-authentication, the problem of long-time revelation of authentication information has been solved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.22-28
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• 2009

As multiprocessors have been widely adopted in embedded systems, task computation energy consumption should be minimized with several low power techniques supported by the multiprocessors. This paper proposes an energy-aware task scheduling algorithm that adopts both dynamic voltage scaling and power shutdown in multiprocessor environments. Considering the timing and energy overhead of power shutdown, the proposed algorithm performs an iterative task assignment and task ordering for multiprocessor systems. In this case, the iterative priority-based task scheduling is adopted to obtain the best solution with the minimized total energy consumption. Total energy consumption is calculated by considering a linear programming model and threshold time of power shutdown. By analyzing experimental results for standard task graphs based on real applications, the resource and timing limitations were analyzed to maximize energy savings. Considering the experimental results, the proposed energy-aware task scheduling provided meaningful performance enhancements over the existing priority-based task scheduling approaches.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.7
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• pp.677-684
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• 2016

With the increase of multimedia information such as image, researches on extracting high-level semantic information from low-level visual information has been realized, and in order to automatically generate this kind of information. Various technologies have been developed. Generally, image retrieval is widely preceded by comparing colors and shapes among images. In some cases, images with similar color, shape and even meaning are hard to retrieve. In this article, in order to retrieve the object in an image, technical value of middle level is converted into meaning value of middle level. Furthermore, to enhance accuracy of segmentation, K-means algorithm is engaged to compute k values for various images. Thus, object retrieval can be achieved by segmented low-level feature and relationship of meaning is derived from ontology. The method mentioned in this paper is supposed to be an effective approach to retrieve images as required by users.