• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.3
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• pp.171-178
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• 2008

Pressure control of hydraulic pump using SRM with pressure predictor and direct torque control method is presented in this paper. Nowadays, high efficiency and high performance motor drive is much interested in hydraulic pump system. But the hydraulic pump system has an inherent defect that its dynamic behavior causes by interaction between the sensor and hydraulic load. It will make low performance of whole system, even unstable and oscillatory. Proposed system integrates pressure predictor and direct instantaneous torque control (DITC). The pressure predictor includes Smith predictor, which is easy to improve unstable or long oscillation in traditional negative feedback control and popular PID control architectures. And DITC method can reduce inherent torque ripple of SRM, and develop smooth torque to load, which can increase stability and improve the torque response of SR drive. So high dynamic performance and stabilization can achieved proposed hydraulic system. At last, the proposed hydraulic system is verified by simulation and experimental results.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.5
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• pp.25-32
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• 2006

This paper proposes a regeneration inverter system, which can regenerate the excessive power form do bus line to ac source for traction system. The proposed regeneration inverter system for dc traction can reduce harmonics which are included to ac current source. The regeneration inverter is operated as two modes. In the regeneration inverter mode, it can recycle regenerative energy caused by decelerating tractions and in the active power filter mode, it can compensate harmonic distortion produced by the rectifier substation. In this paper, the regeneration inverter uses PWM DC/AC inverter algorithm and the active power filter uses p-q theory. From the informative simulation and experimental results, which are performed wiith a prototype rated 3.7[kw], it can expected that the proposed system can be effectively applied in the real traction system rated 100[kw].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.6
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• pp.427-434
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• 2013

In this paper, the design and layout of a 2.5 Gbps arrayed VCSEL driver for optical transceiver having arrayed multi-channel of integrating module is confirmed. In this paper, a 4 channel 2.5 Gbps VCSEL (vertical cavity surface emitting laser) driver array with automatic optical power control is implemented using $0.18{\mu}m$ CMOS process technology that drives a $1550{\mu}m$ high speed VCSEL used in optical transceiver. To enhance the bandwidth of the optical transmitter, active feedback amplifier with negative capacitance compensation is exploited. We report a distinct improvement in bandwidth, voltage gain and operation stability at 2.5Gbps data rate in comparison with existing topology. The 4-CH chip consumes only 140 mW of DC power at a single 1.8V supply under the maximum modulation and bias currents, and occupies the die area of $850{\mu}m{\times}1,690{\mu}m$ excluding bonding pads.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.2
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• pp.139-145
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• 2024

This paper presents the design of a voltage controlled oscillator (VCO) which is one of the key building blocks in modern wireless communication systems with small VCO gain (K_vco) variation. To compensate conventional large K_vco variation, a series varactor bank has been added to the conventional LC-tank with parallel capacitor bank array. And also, in order to achieve excellent phase noise performance while maintaining wide tuning range, a mixed coarse/fine tuning scheme(series varactor array and parallel capacitor array) is chosen. The switched varactor array bank is controlled by the same digital code for switched capacitor array without additional digital circuits. For use at a low voltage of 1.2V, the proposed current reference circuit in this paper used a current reference circuit for safety with the common gate removed more safely. Implemented in a TSMC 0.13㎛ CMOS RF technology, the proposed VCO can be tuned from 4.4GH to 5.3GHz with the K_vco (VCO gain ) variation of less than 9.6%. While consuming 3.1mA from a 1.2V supply, the VCO has -120dBc/Hz phase noise at 1MHz offset from the carrier of the 5.3 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.4
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• pp.748-757
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• 2007

This paper is intended to solve the technical problem that fails in large-capacity induction motor starting due to serious voltage drop during starting period. One induction motor that is established already can reach in steady-state using reactor starting method but the voltage magnitude of PCC (point of common coupling) has dropped down a little. When the same capacity induction motor is installed additionally in the PCC, where the existing induction motor is operating, voltage drop becomes more serious by starting of additional induction motor. As a result, the additional induction motor fails in starting. Therefore, voltage compensation method is proposed so that all of two induction motors can be started completely. First, modeling technique is described in order to implement starting characteristics of large induction motor. And then, this paper proposes strategic starting scheme by proper voltage compensation that use no-load transformer tap control (NLTC) and step voltage regulator (SVR) for starting of two large induction motors successfully and improving the feeding network voltage profile during the starting period. The induction motor discussed in this paper is the pumped induction motor of 2500kVA capacity that is operating by KOWACO (Korea Water Resources Corporation). Modeling and simulation is conducted using PSCAD/EMTDC software.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.3
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• pp.455-464
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• 2019

The sensorless control based on the flux linkage of PM synchronous motors has excellent position estimation characteristics at low speeds. However, a limitation arises because the integrator of flux estimator is saturated by the DC offset generated during the analog to digital conversion(ADC) process of the measured current. In order to overcome this limitation, HPF with a low cutoff frequency is used. However, the estimation performance is deteriorated (Ed- the verb deteriorate already includes the meaning of 'problem') at high speed due to the low cutoff frequency, and increasing the cutoff frequency of the HPF induces further problems of phase leading and initial starting failure at low speeds. In this paper, the cutoff frequency of HPF was synchronized to the operation frequency of the motor: at low speeds the cutoff frequency was set to low in order to reduce the phase leading of the estimated flux, and at high speeds it was set to high to raise the DC offset removal performance. As a result, the operating range was increased by 200%. Furthermore, a phase compensation algorithm is proposed to reduce the phase leading of the HPF to less than 1.5 degrees over the full operating range. The proposed sensorless control algorithm was verified by experiment with a PM synchronous motor for a washing machine.