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Thomas Olsson and Peter Nilsson, "A Digitally controlled PLL for SoC Applications", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 5, pp. 751-760, MAY 2004
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ScienceOn
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Mozhgan Mansuri and Chih-Kong Ken Yang, "A Low-Power Adaptive bandwidth PLL and Clock Buffer With Supply-Noise Compensation", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 11, pp. 1804-1812, NOVEMBER 2003
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Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kerem Ok, Kartikeya Mayaram and Un-Ku Moon, "A Digital PLL with a Stochastic Time-to-Digital Converter" 2006 Symposium on VLSI Circuits Digest of Technical Papers, pp. 31-32, Honolulu, June 2006
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Inchul Hwang, Soonsub Lee, Sangwon Lee, Soowon Kim, "A Digitally Controlled Phase Locked Loop with Fast Locking Scheme for Clock Synthesis Application" 2000 IEEE International Solid-State Circuits Conference, pp. 168-169, 453, San Francisco, Fab. 2000
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Ji-Hoon LIM, Jong-Chan HA, Won-Young JUNG, Yong-Ju KIM, Jae-Kyung WEE, "A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips" IEICE TRANS. ELECTRON., VOL.E90-C, NO.3 MARCH 2007
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Borivoje Nikolic, , Vojin G. Oklobdzija, Vladimir Stojanovic,Wenyan Jia, James Kar-Shing Chiu, and Michael Ming-Tak Leung, "Improved Sense-Amplifier-Bases Flip-Flop: Design and Measurements" IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 6, pp. 876-884, JUNE 2000
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Wei-Hao Chiu, Tai-Shun Chan, and Tsung-Hsien Lin, "A 5.5-GHz 16-mW Fast-locking Frequency Synthesizer in 0.18-m CMOS", IEEE Asian Solid-State Circuits Conference, sec. 17-4, p.p 456-459, November 12-14, 2007
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Kwang-Jin LEE, Hyo-chang KIM, Uk-Rae CHO, Hyun-Geun BYUN, and Suki KIM, "A Low Jitter ADPLL for Mobile Applications", IEICE TRANS. ELECTRON., VOL.E88-C, NO.6 JUNE 2005
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Youn-Sik Park, Bai-Sun Kong and Young-Hyun Jun, " PVT Invariant Single Input-to-Differential Output Converter For High Speed DDR SDRAM" SoC Conference, 2007
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