• Clean Technology
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• v.23 no.1
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• pp.73-79
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• 2017

Recently usage of biomass is increased in pulverized coal power plants for reduction of $CO_2$ emission. Many problems arise when thermal share of the biomass is increased, and milling of the biomasses is one of the most important problems due to their low grindability when existing coal pulverizer is used. Grindability of coal can be measured through the HGI (Hardgrove grindability index) equipment as a standard, but method of measuring biomass grindability has not been established yet. In this study, grinding experiment of coal and biomass was performed using a lab-scale ball mill. One type of coal (Adaro coal) and six biomasses (wood pellet (WP), empty fruit bunch (EFB), palm kernel shell (PKS), walnut shell (WS), torrefied wood chip (TBC) and torrefied wood pellet (TWP)) were used in the experiment. Particle size distributions of the fuels were measured after being milled in various pulverization times. Pulverization characteristics were evaluated by portion of particles under the diameter of $75{\mu}m$. As a result, about 70% of the TBC and TWP were observed to be pulverized to sizes of under $75{\mu}m$, which implies that they can be used as alternative biomass fuels without modification of the existing mill. Other biomass was observed to have low grindability compared with torrefied biomass. Power consumption of the mill for various fuels was measured as well, and the results show that lower power was consumed for torrefied biomasses. This result can be used for characterization of biomass as an alternative fuel for pulverized coal power plants.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.465-469
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.1-9
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• 2009

In this paper, a small area 12-bit 300MSPS CMOS Digital-to-Analog Converter(DAC) is proposed for display systems. The architecture of the DAC is based on a current steering 6+6 segmented type, which reduces non-linearity error and other secondary effects. In order to improve the linearity and glitch noise, an analog current cell using monitoring bias circuit is designed. For the purpose of reducing chip area and power dissipation, furthermore, a noble self-clocked switching logic is proposed. To verify the performance, it is fabricated with $0.13{\mu}m$ thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is $0.26mm^2$ ($510{\mu}m{\times}510{\mu}m$) with 100mW power consumption. The measured INL (Integrated Non Linearity) and DNL (Differential Non Linearity) are within ${\pm}3LSB$ and ${\pm}1LSB$, respectively. The measured SFDR is about 70dB, when the input frequency is 15MHz at 300MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.34-41
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• 2011

This paper presents a wide tuning range, fine-resolution DCO (Digitally Controlled Oscillator) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. To cover the wide tuning range, an automatic three-step coarse tuning scheme is proposed. The DCO total frequency tuning range is 1.4 GHz (2.1 GHz to 3.5 GHz), it is 58 % at 2.4 GHz. An effective frequency resolution is 0.14 kHz/LSB. The proposed DCO is implemented in 0.13 ${\mu}m$ CMOS process. The total power consumption is 6.6 mW from a 1.2 V supply voltage. The phase noise of the DCO output at 2.4 GHz is -120.67 dBc/Hz at 1 MHz offset.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.56-63
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• 2012

The WBAN technology means a short distance wireless network which provides each device interactive communication by connecting devices inside and outside of body. Standardization on the physical layer, data link layer, network layer and application layer is in progress by IEEE 802.15.6 TG BAN. Wireless body area network is usually configured in energy efficient using sensor and zigbee device due to the power limitation and the characteristics of human body. Wireless sensor network consist of sensor field and sink node. Sensor field are composed a lot of sensor node and sink node collect sensing data. Wireless sensor network has capacity of the self constitution by protocol where placed in large area without fixed position. Mobile sink node distribute energy consumption therefore network life time was increased than fixed sink node. The energy efficient is important matter in wireless body area network because energy resource was limited on sensor node. In this paper we proposed cluster topology algorithm for efficient data transmission in wireless body area network based mobile sink. The proposed algorithm show good performance under the advantage of grid routing protocol and TDMA scheduling that minimized overlap area on cluster and reduced amount of data on cluster header in error prone wireless sensor network based on mobile sink.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.184-193
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• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.80-86
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• 2014

A low-noise readout circuit is studied for 2-D capacitive microbolometer focal plane arrays (FPAs). In spite of the merits of the integration method, a simple and effective pixelwise readout circuit without integration is used for input circuit because of a small pixel size and narrow noise bandwidth. To reduce the power consumption and the kT/C noise, which is the dominant noise of the capacitive microbolometer FPAs with small capacitance, a new correlated double sampling (CDS) is used for columnwise circuit. The proposed circuit has been designed using a $0.35-{\mu}m$ 2-poly 4-metal CMOS process for a microbolometer array with a pixel size of $50{\mu}m{\times}50{\mu}m$. The proposed circuit effectively reduces the kT/C noise and the other low-frequency noise of microbolometer, and the noise characteristics of the fabricated chip have been verified by measurements. The rms noise voltage of the proposed circuit is reduced from 30 % to 55 % compared to that of the simple readout input circuit, and the noise equivalent temperature difference (NETD) of the proposed circuit is very low value of 21.5 mK.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.16-24
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• 2002

This work describes a 10b 120 MSample/s CMOS pipelined A/D converter(ADC) based on a merged-capacitor switching(MCS) technique for high signal processing speed and high resolution. The proposed ADC adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area, and employs a MCS technique which improves sampling rate and resolution reducing the number of unit capacitor used in the multiplying digital-to-analog converter (MDAC). The proposed ADC is designed and implemented in a 0.25 um double-poly five-metal n-well CMOS technology. The measured differential and integral nonlinearities are within ${\pm}$0.40 LSB and ${\pm}$0.48 LSB, respectively. The prototype silicon exhibits the signal-to-noise-and-distortion ratio(SNDR) of 58 dB and 53 dB at 100 MSample/s and 120 MSample/s, respectively. The ADC maintains SNDR over 54 dB and the spurious-free dynamic range(SFDR) over 68 dB for input frequencies up to the Nyquist frequency at 100 MSample/s. The active chip area is 3.6 $mm^2$(＝ 1.8 mm ${\times}$ 2.0 mm) and the chip consumes 208 mW at 120 MSample/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.83-89
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• 2006

This paper describes the design of I/Q channel 12bit Digital-to-Analog Converter(DAC) which shows the conversion rate of 120MHz and the power supply of 3.3V with 0.35um CMOS n-well 1-poly 4-metal process for advanced wireless transceiver. The proposed DAC utilizes 4-bit thermometer decoder with 3 stages for minimum glitch energy and linearity error. Also, using a optimized 4bit thermometer decoder for the decrement of the chip area. Integral nonlinearity(INL) of ${\pm}1.6LSB$ and differential nonlinearity(DNL) of ${\pm}1.3LSB$ have been measured. In single tone test, the ENOB of the proposed 12bit DAC is 10.5bit and SFDR of 73dB(@ Fs=120MHz, Fin=1MHz) is measured, respectively. Dual-tone test SFDR is 61 dB (@ Fs=100MHz, Fin=1.5MHz, 2MHz). Glitch energy of 31 pV.s is measured. The converter consumes a total of 105mW from 3.3-V power supply.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.36 no.5
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• pp.487-493
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• 2012

We present interferometric modulators that reproduce RGB colors through the selective actuation of mechanically coupled mirror arrays having identical air gaps. The conventional transmittive interferometric modulators need additional backlights, which leads to high power consumption. The previous reflective interferometric modulators using ambient lights need three different air gaps for reproducing the three RGB colors, thus giving rise to process complexity. For process simplicity, we propose the use of reflective interferometric modulators that are capable of producing green, blue, red, and black colors with the aid of mechanically coupled mirrors with identical air gaps. In an experimental study, the present interferometric modulators reproduce green, blue, and red colors at the switching modes (000), (010), and (101). The spectrum peaks for the colors are measured at the wavelengths $511{\pm}5nm$, $478{\pm}3nm$, and $644{\pm}9nm$, respectively, with the bandwidths being $60{\pm}1nm$, $45{\pm}2nm$, and $105{\pm}4nm$, respectively; further, the maximum intensities of the colors are $77{\pm}5%$, $73{\pm}2%$, and $81{\pm}5%$, respectively. The black spectrum is measured below the intensity of $27{\pm}0%$. Thus, we experimentally demonstrate the color reproduction capability of interferometric modulators fabricated by using a simple process.