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I/Q channel 12-Bit 120MHz CMOS D/A Converter for WLAN  

Ha, Sung-Min (Dept. of Electronic Engineering, Inha University)
Nam, Tae-Kyu (Dept. of Electronic Engineering, Inha University)
Seo, Sung-Uk (Dept. of Electronic Engineering, Inha University)
Shin, Sun-Hwa (Dept. of Electronic Engineering, Inha University)
Joo, Chan-Yang (Dept. of Electronic Engineering, Inha University)
Yoon, Kwang-S. (Dept. of Electronic Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.11, 2006 , pp. 83-89 More about this Journal
Abstract
This paper describes the design of I/Q channel 12bit Digital-to-Analog Converter(DAC) which shows the conversion rate of 120MHz and the power supply of 3.3V with 0.35um CMOS n-well 1-poly 4-metal process for advanced wireless transceiver. The proposed DAC utilizes 4-bit thermometer decoder with 3 stages for minimum glitch energy and linearity error. Also, using a optimized 4bit thermometer decoder for the decrement of the chip area. Integral nonlinearity(INL) of ${\pm}1.6LSB$ and differential nonlinearity(DNL) of ${\pm}1.3LSB$ have been measured. In single tone test, the ENOB of the proposed 12bit DAC is 10.5bit and SFDR of 73dB(@ Fs=120MHz, Fin=1MHz) is measured, respectively. Dual-tone test SFDR is 61 dB (@ Fs=100MHz, Fin=1.5MHz, 2MHz). Glitch energy of 31 pV.s is measured. The converter consumes a total of 105mW from 3.3-V power supply.
Keywords
CMOS; D/A converter; WLAN; Thermometer decoder;
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