I/Q channel 12-Bit 120MHz CMOS D/A Converter for WLAN

무선랜용 I/Q 채널 12bit 120MHz CMOS D/A 변환기 설계

  • Ha, Sung-Min (Dept. of Electronic Engineering, Inha University) ;
  • Nam, Tae-Kyu (Dept. of Electronic Engineering, Inha University) ;
  • Seo, Sung-Uk (Dept. of Electronic Engineering, Inha University) ;
  • Shin, Sun-Hwa (Dept. of Electronic Engineering, Inha University) ;
  • Joo, Chan-Yang (Dept. of Electronic Engineering, Inha University) ;
  • Yoon, Kwang-S. (Dept. of Electronic Engineering, Inha University)
  • 하성민 (인하대학교 전자공학과) ;
  • 남태규 (인하대학교 전자공학과) ;
  • 서성욱 (인하대학교 전자공학과) ;
  • 신선화 (인하대학교 전자공학과) ;
  • 주찬양 (인하대학교 전자공학과) ;
  • 윤광섭 (인하대학교 전자공학과)
  • Published : 2006.11.25

Abstract

This paper describes the design of I/Q channel 12bit Digital-to-Analog Converter(DAC) which shows the conversion rate of 120MHz and the power supply of 3.3V with 0.35um CMOS n-well 1-poly 4-metal process for advanced wireless transceiver. The proposed DAC utilizes 4-bit thermometer decoder with 3 stages for minimum glitch energy and linearity error. Also, using a optimized 4bit thermometer decoder for the decrement of the chip area. Integral nonlinearity(INL) of ${\pm}1.6LSB$ and differential nonlinearity(DNL) of ${\pm}1.3LSB$ have been measured. In single tone test, the ENOB of the proposed 12bit DAC is 10.5bit and SFDR of 73dB(@ Fs=120MHz, Fin=1MHz) is measured, respectively. Dual-tone test SFDR is 61 dB (@ Fs=100MHz, Fin=1.5MHz, 2MHz). Glitch energy of 31 pV.s is measured. The converter consumes a total of 105mW from 3.3-V power supply.

본 논문에서는 무선통신용 송수신기에 집적화할 수 있도록 $0.35{\mu}m$ CMOS n-well 1-poly 4-metal 공정을 이용하여 3.3V의 전원 전압으로 동작하는 I/Q 채널 12비트 120MHz 전류구동 D/A 변환기를 설계하였다. 설계된 12비트 D/A 변환기는 4비트 온도계 디코더를 3단 구성하여 글리치 에너지와 선형오차 특성을 최소화하였다. 측정된 선형오차인 INL/DNL은 각각 ${\pm}1.5LSB$, ${\pm}1.3LSB$이며, 글리치 에너지는 31pV.s 로 측정되었고, 전력소모는 105mW이다. 샘플링 및 입력주파수가 각각 120MHz, 1MHz일 때, 싱글 톤 테스트에서 유효비트수는 10.5비트로 측정되었다. 듀얼 톤 테스트에서 1MHz/1.1MHz의 기저대역신호는 0.9MHz/1.2MHz의 영상신호 차이가 -63dB 나타나는 것으로 측정되었다.

Keywords

References

  1. K. O'Sullivan, C. Gorman, M. Hennessy, and V. Callaghan, 'A 12-bit 320-MS/s Current-Steering CMOS D/A converter in $0.44mm^2$,' IEEE J. Solid-State Circuits, vol. 39, pp.1064-1072, Jul 2004 https://doi.org/10.1109/JSSC.2004.829923
  2. Y. Nakamura, T. Miki, A. Maede, H. Kondoh, and N. Yazawa, 'A 10-b 70-MS/s CMOS D/A converter,' IEEE J. Solid-State Circuits, vol. 26, pp.637-642, Apr. 1991 https://doi.org/10.1109/4.75066
  3. T. Wu, C. Jih, J. Chen, and C. Wu, 'Alow glitch 10-bit 75-MHz CMOS video D/A converter,' IEEE J. Solid-State Circuits, vol. 30, pp. 68-78, Jan. 1995 https://doi.org/10.1109/4.350191
  4. P. Hendriks, 'Specifying communications D/A converters,' IEEE Spectrum, vol. 34, pp.57-69, July 1997 https://doi.org/10.1109/MSPEC.1997.8054562
  5. Ki-Hong Ryu, Sung Young Park and Kwang Sub Yoon, 'A 3.3V 12-Bit High-Speed Current Cell Matrix CMOS D/A converter,' J. Korean Phys. Soc, vol.39, No.1, pp. 127-131, July, 2001
  6. A. Van den Bosch, Marc A. F. Borrenmans, M. Steyaert and W. Sansen, 'A 10bit 1GSample/s Nyquist Current Steering CMOS D/A converter,' IEEE J. Solid-State Circuits, vol.36, No.3, pp.315-324, Mar, 2001 https://doi.org/10.1109/4.910469
  7. Yijun Zhou and jiren Yuan, 'An 8-Bit 100-MHz Low Glitch Interpolation D/A converter,' ISCAS, vol.4, pp.116-119, May, 2001 https://doi.org/10.1109/ISCAS.2001.922184
  8. Jussi Pirkkalaniemi, Mikko Waltari, Marko Kosunen, Lauri Sumanen and Kari Halonen, 'A 14-bit, 40MS/s D/A converter with Current Mode Deglitcher,' ISCAS, vol.1, pp.I-121-I-124, 2002
  9. M. Pelgrom, A. Duinmaijer, and A. Welbers, 'Matching Properties of MOS Transistors,' IEEE J. Solid-State Circuits, vol.24, No.5 pp.1433-1440, Oct. 1989 https://doi.org/10.1109/JSSC.1989.572629
  10. B. Razavi, Principle of Data Conversion System Design, IEEE Press, 1995
  11. B. Schafferer, R. Adams, 'A 3V CMOS 400mW 14b L4GS/s DAC for Multi-Carrier Applications,' IEEE ISSCC, Feb. 2004
  12. Q. Huang, P. andrea Francese, C. Martelli, J. Nielsen, 'A 200MS/s 14b 97mW DAC in $0.18{\mu}m$ CMOS,' ISSCC, session 20, Feb, 2004 https://doi.org/10.1109/ISSCC.2004.1332745
  13. K. Doris, J. Briaire, D. Leenaerts, M. Vertregt, A. van Roermund, 'A 12b 500MS/s DAC with > 70dB SFDR up to 120MHz in $0.18{\mu}m$ CMOS,' ISSCC, session 6, Feb, 2005