• Transactions of the Korean Society of Mechanical Engineers B
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• v.36 no.4
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• pp.457-463
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• 2012

Current refrigerators are designed to have thin doors and walls to facilitate user convenience and increase inner storage space. However, the thin doors and walls gives rise to the problem of dew generation on the outer surface of a refrigerator due to a large critical temperature difference between the outer wall and the room air; So far, an electric heater is commonly used for making the dew to evaporate; in this case, the heater inevitably requires additional electrical power. We propose a new approach to reduce the dew generation in a refrigerator by redesigning the gasket and varying the thickness of the inner case of the refrigerator. The results of simulations performed in this study indicate that the surface temperature in the region where dew was generated was increased by approximately $0.39{\sim}3.07^{\circ}C$ without the use of a heater.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.53-60
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• 2004

This work describes a l0b 150 MSample/s CMOS pipelined A/D converter (ADC) based on advanced bootsuapping techniques for higher input bandwidth than a sampling rate. The proposed ADC adopts a typical multi-step pipelined architecture, employs the merged-capacitor switching technique which improves sampling rate and resolution reducing by $50\%$ the number of unit capacitors used in the multiplying digital-to-analog converter. On-chip current and voltage references for high-speed driving capability of R & C loads and on-chip decimator circuits for high-speed testability are implemented with on-chip decoupling capacitors. The proposed AU is fabricated in a 0.18 um 1P6M CMOS technology. The measured differential and integral nonlinearities are within $-0.56{\~}+0.69$ LSB and $-1.50{\~}+0.68$ LSB, respectively. The prototype ADC shows the signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. The active chip area is 2.2 mm2 (= 1.4 mm ${\times}$ 1.6 mm) and the chip consumes 123 mW at 150 MSample/s.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.51-57
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• 2015

In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.89-94
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• 2008

In this paper, a cascade of a wideband amplifier and a high-Q bandpass filter (BPF) has been realized in a 0.18mm CMOS technology for the applications of subsampling direct-conversion receivers. The wideband amplifier is designed to obtain the -3dB bandwidth of 5.4GHz, and the high-Q BPF is designed to select a 2.4GHz RF signal for the Bluetooth specifications. The measured results demonstrate 18.8dB power gain at 2.34GHz with 31MHz bandwidth, corresponding to the quality factor of 75. Also, it shows the noise figure (NF) of 8.6dB, and the broadband input matching (S11) of less than -12dB within the bandwidth. The whole chip dissipates 64.8mW from a single 1.8V supply and occupies the area of $1.0{\times}1.0mm2$.

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2017.04a
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• pp.160-160
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• 2017

자동화 기술을 통한 한국형 스마트팜의 발전이 비약적으로 이루어지고 있는 가운데 무인화를 위한 지능적인 스마트 시설환경 관찰 및 분석에 대한 요구가 점점 증가 하고 있다. 스마트 시설환경에서 취득 가능한 시계열 데이터는 온도, 습도, 조도, CO2, 토양 수분, 환기량 등 다양하다. 시스템의 경계가 명확함에도 해당 속성의 특성상 타임도메인과 공간도메인 상에서 정확한 추정 또는 예측이 난해하다. 시설 환경에 접목이 증가하고 있는 지능형 관리 기술 구현을 위해선 시계열 공간 데이터에 대한 신속하고 정확한 정량화 기술이 필수적이라 할 수 있다. 이러한 기술적인 요구사항을 해결하고자 시도되는 다양한 방법 중에서 공간 분해능 향상을 위한 다지점 계측 메트릭스를 실험적으로 구성하였다. $50m{\times}100m$의 단면적인 연동 딸기 온실을 대상으로 $3{\times}3{\times}3$의 3차원 환경 인자 계측 매트릭스를 설치하였다. 1 Hz의 주기로 4가지 환경인자(온도, 습도, 조도, CO2)를 계측하였으며, 계측 하는 시점과 동시에 병렬적으로 공간통계법을 이용하여 미지의 지점에 대한 환경 인자들을 실시간으로 추정하였다. 선행적으로 50 cm 공간 분해능에 대응하기 위하여 Kriging interpolation법을 횡단면에 대하여 분석한 후 다시 종단면에 대하여 분석하였다. 3 Ghz에 해당하는 연산 능력을 보유한 컴퓨터에서 1초 동안 획득한 데이터에 대한 분석을 마치는데 소요되는 시간이 15초 내외로 나타났다. 이는 해당 알고리즘의 매우 높은 시간 복잡도(Order of $O=O^3$)에 기인하는 것으로 다양한 시설 환경의 관리 방법론에 적절히 대응하기에 한계가 있다 할 수 있다. 실시간으로 시간 복잡도가 높은 연산을 수행하기 위한 기술적인 과제를 해결하고자, 근래에 관심이 증가하고 있는 NVIDIA 사에서 제공하는 CUDA 엔진과 Apple사의 제안을 시작으로 하여 공개 소프트웨어 개발 컨소시엄인 크로노스 그룹에서 제공하는 OpenCL 엔진을 비교 분석하였다. CUDA 엔진은 GPU(Graphics Processing Unit)에서 정보 분석 프로그램의 연산 집약적인 부분만을 담당하여 신속한 결과를 산출할 수 있는 라이브러리이며 해당 하드웨어를 구비하였을 때 사용이 가능하다. 반면, OpenCL은 CUDA 엔진이 특정 하드웨어에서 구동이 되는 한계를 극복하고자 하드웨어에 비의존적인 라이브러리를 제공하는 것이 다르며 클러스터링 기술과 연계를 통해 낮은 하드웨어 성능으로 인한 단점을 극복하고자 하였다. 본 연구에서는 CUDA 8.0(https://developer.nvidia.com/cuda-downloads)버전과 Pascal Titan X(NVIDIA, CA, USA)를 사용한 방법과 OpenCL 1.2(https://www.khronos.org/opencl/)버전과 Samsung Exynos5422 칩을 장착한 ODROID-XU4(Hardkernel, AnYang, Korea)를 사용한 방법을 비교 분석하였다. 50 cm의 공간 분해능에 대응하기 위한 4차원 행렬($100{\times}200{\times}5{\times}4$)에 대하여 정수 지수화를 위한 Quantization을 거쳐 CUDA 엔진과 OpenCL 엔진을 적용한 비교한 결과, CUDA 엔진은 1초 내외, OpenCL 엔진의 경우 5초 내외의 연산 속도를 보였다. CUDA 엔진의 경우 비용측면에서 약 10배, 전력 소모 측면에서 20배 이상 소요되었다. 따라서 우선적으로 OpenCL 엔진 기반 하드웨어 가속 기술 최적화 연구를 통해 스마트 시설환경 실시간 시뮬레이션 기술 도입을 위한 기술적 과제를 풀어갈 것이다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.28 no.5
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• pp.179-184
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• 2018

To lessen oxygen concentrations in a wafer through modifying the length of graphite heaters, we investigated the influence of relative distance from heater to quartz crucible on temperature profile of hot-zone in Czochralski silicon-crystal growth by simulation. In particular, ATC temperature and power profiles as a function of different ingot body positions were investigated for five different heater designs; (a) typical side heater (SH), (b) short side heater-up (SSH-up), (c) short side heater-low (SSH-low), (d) bottom heater without side heater (Only-BH), and (e) side heater with bottom heater (SH + BH). It was confirmed that lower short side heater exhibited the highest ATC temperature, which was attributed to the longest distance from triple point to heater center. In addition, for the viewpoint of energy efficiency, it was observed that the typical side heater showed the lowest power because it heated more area of quartz crucible than that of others. This result provides the possibility to predict the feed-forward delta temperature profile as a function of various heater designs.

• Journal of the Korea Institute of Building Construction
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• v.11 no.3
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• pp.283-291
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• 2011

As the construction industry has recently been transformed by the emergence of ubiquitous and intelligent technology, there have been major changes in the management methods employed. Specifically, next-generation construction management systems have been developed that collect and analyze many pieces of information in real time by using various wireless sensors and networks. The purpose of this study is to understand the current status of Ubiquitous Sensor Networks (USN) in the construction sector, and to gain fundamental data for a system of measuring concrete curing temperature in a construction site that employs a USN. By investigating the application status of USN, it was confirmed that USN has mainly been applied to the maintenance of facilities, safety management, and quality control. In addition, a field experiment in which the curing temperature of concrete was measured using a USN was carried out to evaluate two systems with wireless sensor networks, and the applicability of these systems on site was confirmed. However, it is estimated that the embedded wireless sensor type is affected by metal equipment on site, internal battery of sensor and concrete depth, and studies to provide more stable system by USN are thus required.

• The KIPS Transactions:PartC
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• v.13C no.5 s.108
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• pp.541-548
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• 2006

Sensor network is a network for realizing the ubiquitous computing circumstances, which aggregates data by means of observation or detection deployed at the inaccessible places with the capacities of sensing and communication. To realize this circumstance, data which sensor nodes gathered from sensor networks are delivered to users, in which it is required to encrypt the data for the guarantee of secure communications. Therefore, it is needed to design key management scheme for encoding appropriate to the sensor nodes which feature continual data transfer, limited capacity of computation and storage and battery usage. We propose a key management scheme which is appropriate to sensor networks organizing hierarchical architecture. Because sensor nodes send data to their parent node, we can reduce routing energy. We assume that sensor nodes have different security levels by their levels in hierarchy. Our key management scheme provides different key establishment protocols according to the security levels of the sensor nodes. We reduce the number of sensor nodes which share the same key for encryption so that we reduce the damage by key exposure. Also, we propose key update protocols which take different terms for each level to update established keys efficiently for secure data encoding.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.1
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• pp.29-36
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• 2009

In this paper, the design and implementation of LNA and down-mixer using 90 nm CMOS process are presented for 60 GHz band WPAN receiver. In order to extract characteristics of the transistor used to design each elements under the optimum bias conditions, the S-parameter of the manufactured cascode topology was measured and the effect of the RF pad was removed. Measured results of 3-stages cascode type LNA the gain of 25 dB and noise figure of 7 dB. Balanced type down-mixer with a balun at LO input port shows the conversion gain of 12.5 dB within IF frequency($8.5{\sim}11.5\;GHz$) and input PldB of -7 dBm. The size and power consumption of LNA and down-mixer are $0.8{\times}0.6\;mm^2$, 43 mW and $0.85{\times}0.85\;mm^2$, 1.2 mW, respectively.