Browse > Article
http://dx.doi.org/10.5573/ieie.2015.52.5.051

A Design of a Reconfigurable 4th Order ΣΔ Modulator Using Two Op-amps  

Yang, Su-Hun (Department of Electronic Engineering, Inha University)
Choi, Jeong-Hoon (Department of Electronic Engineering, Inha University)
Yoon, Kwang Sub (Department of Electronic Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.52, no.5, 2015 , pp. 51-57 More about this Journal
Abstract
In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.
Keywords
Bio signal; ${\Sigma}{\Delta}$modulator; low power; reuse; KT/C noise;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Zhenglin Yang, Libin Yao, Yong Lian, "A 0.5-V $35-{\mu}W$ 85-dB DR Double-Sampled ${\Delta}{\Sigma}$ Modulator for Audio Applications" JSSC, vol.47, pp. 722-735, 2012.
2 H.D. Roh, H. J. Kim, Y. K. Choi, J. J. Roh, Y. G. Kim, J. K. Kwon, "A 0.6-V Delta?Sigma Modulator With Subthreshold-Leakage Suppression Switches" Circuits and Systems II, vol. 56, pp. 825-829, 2010.
3 Bonizzoni, E. ; Perez, A.P. ; Maloberti, F. ; Garcia-Andrade, M. "Third-order ${\Sigma}{\Delta}$ modulator with 61-dB SNR and 6-MHz bandwidth consuming 6 mW", analg Integr.Circuits Signal Process, vol. 66, no. 3, pp. 381-388, Sep. 2010.
4 Pena-Perez, A, Bonizzoni, E, Maloberti, F. "A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order ${\Sigma}{\Delta}$ Modulator" JSSC, vol. 47, pp. 2107-2118.
5 R. Schreier, G. C. Temes. "Understanding Delta-Sigma Data Converters" New-York, Wiley-IEEE Press 2005.
6 P. J. Quinn, Arthur H.M.Van Roermund "Switched-Capacitor Techniques for High- Accuracy Filter and ADC design" Dordrecht, Springer 2007.
7 Y.K. Choi, J.J. Roh, H. D. Roh, H. S. Nam, S. J. Lee, "A 99-dB DR Fourth-Order Delta?Sigma Modulator for 20-kHz Bandwidth Sensor Applications",Instrumentation and Measurement , vol. 58, pp. 2264-2274, 2009.   DOI   ScienceOn
8 Zeller, S. ; Muenker, C.; Weigel, R. ; Ussmueller, U., "A 0.039 mm ^2 Inverter-Based 1.82 mW 68.6-dB-SNDR 10 MHz-BW CT-\Sigma \Delta -ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques", JSSC, vol.49, pp. 1548-1560