• The Journal of the Korea Contents Association
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• v.6 no.3
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• pp.38-45
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• 2006

A dual-level low voltage differential signalling (DLVDS) circuit is proposed aiming at reducing transmission lines for a LCD driver IC. We apply two data to the proposed DLVDS circuit as inputs. Then, the transmitter converts two inputs to two kinds of fully differential signals. In this circuit, two transmission lines are sufficient to transfer two inputs while keeping the LVDS feature. However, the circuit has a common mode bias fluctuation due to difference of the input bias and the reference bias. We compensate the common mode bias fluctuation using a feedback circuit of the current source bias. The receiver recovers the original input data through a level decoding circuit. We fabricated the proposed circuit using $0.25{\mu}m$ CMOS technology. The simulation results of proposed circuit shows 1-Gbps/2-line data rate and 35mW power consumption at 2.5V supply voltage, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.9
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• pp.1928-1934
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• 2009

This paper proposes a power management scheme for sensor nodes in wireless sensor networks based on sensor node operating system supporting the sensor transparency, which can turn off the sensors when the MCU is in sleep mode. We classify the sensors in two types, that is, event sensors and polling sensors, to be able to decide whether the sensor is a type of sensors whose power supply can be turned off or not, and we design a new scheduler to support recognition of those different types of sensors. Implementing and evaluation of the scheduler and the power manager supporting sensor transparency are shown based on Nano-Q+.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.785-792
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• 2012

In this paper, a current-voltage characteristics of n-channel junctionless and inversion mode(IM) MuGFET, and p-channel junctionless and accumulation mode(AM) MuGFET has been measured and analyzed for the application in high speed and low power switching devices. From the variation of the threshold voltage and the saturation drain current with the substrate bias voltages, their variations in IM devices are larger than junctionless devices for n-channel devices, but their variations in junctioness devices are larger than AM devices for p-channel devices. The variations of transconductance with substrate biases are more significant in p-channel devices than n-channel devices. From the characteristics of subthreshold swing, it was observed that the S value is almost independent on the substrate biases in n-channel devices and p-channel junctionless devices but it is increased with the increase of the substrate biases in p-channel AM devices. For the application in high speed and low power switching devices using the substrate biases, IM device is better than junctionless devices for n-channel devices and junctionless device is better than AM devices for p-channel devices.

• Proceedings of the Korea Information Processing Society Conference
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• 2016.04a
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• pp.903-906
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• 2016

최근 사물인터넷(IoT, Internet of Things)관련 기술의 발전 및 서비스 산업의 급속한 발전으로 센서 장치에 대한 수요가 증가하고 있다. 센서 장치는 사물인터넷 플랫폼과의 연동을 위한 통신 인터페이스를 필수로 지원하여야 하며, 그 외에 다양한 센서들의 연동 인터페이스와 소비 전력을 모두 고려하여 하드웨어 및 소프트웨어의 설계가 이루어져야 한다. 이와 같이 센서 장치는 베터리 소비를 최적화하여 모든 기능이 구현되어야 하므로 기능상의 제약이 많이 따른다. 시간 동기화를 위해 사물인터넷 플랫폼에서 송신하는 동기 메시지를 수신하기 위해 슬립모드를 지원하는 경우 센서 장치가 항상 깨어 있어야하므로 저전력으로 동작 할 수 없는 어려움이 따른다. 따라서 데이터를 센싱하는 주기에 맞춰 시간 동기화를 진행하는 프로토콜 및 지연 시간 계산 방안을 제시하고 이에 따른 기존 프로토콜들과 비교하여 경량화한 알고리즘을 제안한다. 향후 시간 동기화 프로토콜의 호환을 위해 CoAP 규격과 연동 될 수 있는 연구가 필요하다.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.1
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• pp.70-77
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• 2005

A new converter to transfer energy from a low-voltage AC current source to a battery is proposed. It is focused to find operational modes of the converter. The low-voltage AC current source is an equivalent of the piezoelectric generator, which converts the mechanical energy to the electric energy. The converter consists of a full-bridge MOSFET rectifier and a MOSFET boost converter in order to make the converter small and efficient. The operational principle and modes of the converter are investigated with the consideration of effects of the parasitic capacitances of MOSFETs and diode. The results are proved with simulation studies using PSIM and Pspice.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.9
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• pp.1027-1034
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• 2014

We present the Low Power Broadband Low noise amplifier(LNA) that can be applied a whole bandwidth from 3G to 4G LTE. This multi input LNA was designed to steadily amplify through a multi input method regardless the size of the input signal and operate on a wide range of frequency band from a standard 3G CDMA band 1.2GHz to LTE band 2.5GHz. The designed LNA consumes an average of 6mA on a 1.2V power supply and this was affirmed using computer simulation tests. The amplification which was corresponded to the lowest input signal is at a maximum of 20dB and was able to obtain the minimum value of the gain of -10dB. The Noise figure is less than 3dB at a High-gain mode and is less than 15dB at a Low-gain mode.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.8
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• pp.959-965
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• 2019

In this paper, we design a low noise amplifier to support ka-band satellite communication systems using 65-nm RFCMOS process. The proposed low noise amplifier is designed with high-gain mode and low-gain mode, and is designed to control the gain according to the magnitude of the input signal. In order to reduce the power consumption, the supply voltage of the entire circuit is limited to 1 V or less. We proposed the gain control circuit that consists of the inverter structure. The 3D EM simulator is used to reduce the size of the circuit. The size of the designed amplifier including pad is $0.33mm^2$. The fabricated amplifier has a -7 dB gain control range in 3 dB bandwidth and the reflection coefficient is less than -6 dB in high gain mode and less than -15 dB in low gain mode.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1371-1378
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• 2009

We propose a low-power eFuse one-time programmable (OTP) memory cell based on a logic process. The eFuse OTP memory cell uses separate transistors optimized at program and read mode, and reduces an operation current at read mode by reducing parasitic capacitances existing at both WL and BL. Asynchronous interface, separate I/O, BL SA circuit of digital sensing method are used for a low-power and small-area eFuse OTP memory IP. It is shown by a computer simulation that operation currents at a logic power supply voltage of VDD and at I/O interface power supply voltage of VIO are 349.5${\mu}$A and 3.3${\mu}$A, respectively. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18${\mu}$m generic process is 300 ${\times}$557${\mu}m^2$.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.279-280
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• 2013

본 논문에서는 3상 양방향 절연형 인터리브드 DC-DC 컨버터의 병렬 제어기법에 대해 기술한다. 대전력 적용 시, DC-DC 컨버터를 단독으로 운전하는 것이 아닌 병렬로 연결하여 운전을 하게 되는데 이때 발생하는 전류의 불평형을 해결하기 위하여 부스트 모드와 벅 모드에서 저전압측의 전압을 제어하는 전압제어기에 각 컨버터의 전류차를 보상하는 전류제어기를 제안하였며 각 모드에서 전류의 불평형이 보상되는 것을 실험을 통해 검증하였다.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.199-200
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• 2014

본 논문에서는 저 용량에서 많이 사용되는 임계 도통 모드 부스트 역률 보상 회로의 새로운 제어 방법을 제안한다. 제안하는 제어 방법은 임계 도통 모드로 동작 시에 회로의 주요 파형들을 수식적으로 분석하여 입력 전류가 입력 전압을 추종할 수 있는 최적의 온-시간을 도출하는 방식이다. 100W 급 하드웨어를 통하여 제안하는 제어 방법의 실험 결과를 검증하였다.