• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.53-60
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• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.135-144
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• 2003

This work proposes on-chip full CMOS current and voltage references for high-speed mixed-mode circuits. The proposed current reference circuit uses a digital-domain calibration method instead of a conventional analog calibration to obtain accurate current values. The proposed voltage reference employs internal reference voltage drivers to minimize the high-frequency noise from the output stages of high-speed mixed-mode circuits. The reference voltage drivers adopt low power op amps and small- sized on-chip capacitors for low power consumption and small chip area. The proposed references are designed, laid out, and fabricated in a 0.18 um n-well CMOS process and the active chip area is 250 um x 200 um. The measured results show the reference circuits have the power supply variation of 2.59 %/V and the temperature coefficient of 48 ppm/$^{\circ}C$ E.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.3 s.345
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• pp.27-31
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• 2006

Millimeter over Fiber (MMoF) technique modulates millimeter wave signal optically to transmit it through an optical fiber for long distances with small loss. MMoF system usually uses optical single sideband (OSSB) modulation scheme to reduce fiber chromatic dispersion and obtain high bandwidth efficiency. The optical link of MMoF system using OSSB is treated as a nonlinear amplifier, and the AM/AM characteristic function of the amplifier is a Bessel function of the first kind of order 1. In this paper, we investigate the performance of OFDM MMoF system considering nonlinearity of OSSB modulation. We estimate a power of the nonlinear distortion noise to analyze the theoretical bit error rate(BER), and perform a simulation to verify the theoretical BER.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.227-228
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• 2006

In this paper, we introduce the design and fabrication of 60 GHz low noise amplifier MMIC for IEEE802.15.3c WPAN system. The 60 GHz LNA was designed using ETRI's $0.12{\mu}m$ PHEMT process. The PHEMT shows a peak transconductance ($G_{m,peak}$) of 500 mS/mm, a threshold voltage of -1.2 V, and a drain saturation current of 49 mA for 2 fingers and $100{\mu}m$ total gate width (2f100) at $V_{ds}$=2 V. The RF characteristics of the PHEMT show a cutoff frequency, $f_T$, of 97 GHz, and a maximum oscillation frequency, $f_{max}$, of 166 GHz. The performances of the fabricated 60 GHz LNA MMIC are operating frequency of $60.5{\sim}62.0\;GHz$, small signal gain ($S_{21}$) of $17.4{\sim}18.1\;dB$, gain flatness of 0.7 dB, an input reflection coefficient ($S_{11}$) of $-14{\sim}-3\;dB$, output reflection coefficient ($S_{22}$) of $-11{\sim}-5\;dB$ and noise figure (NF) of 4.5 dB at 60.75 GHz. The chip size of the amplifier MMIC was $3.8{\times}1.4\;mm^2$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.4
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• pp.28-34
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• 1975

텔레비젼 수신용 안테나로써 가장 널리 사용되고있는 Yagi안테나는 구조가 간단하고 지향성 이득등이 좋으나 방사주파수에 대한 반파장길이의 소자를 사용하므로 칫수가 커지고 주파수대역이 좁다. 따라서 설치 취급등에 불편을 느낄 경우가 많다. 한편 최근 일반적으로 아무곳에서나 용이하계 설치할 수 있을만큼 소형이면서 화질이 좋은 수상이 가능한 수신안테나에 대한 요망이 커지고 있는데 본 연구에서는 그 파장에 비해서 소형인 폴디드·다이폴 안테나 소자 2개를 좁은 간격으로 배열하고 이들을 이상결합하므로써 VHF텔레비젼전파의 고채널 주파수대에서 비교적 양한 단일지향성을 얻고 있다. 본 안테나에 능동소자를 이용한 저잡음광대역증폭기를 삽입한다면 다소자 Yagi안테나에 비나될 전후방비를 갖는위에 그의 이득도 크게 증가되어 일반수상안테나로 뿐만 아니라 고우스트 방지용실내안테나로서 상당한 기여틀 할것으로 생각된다. The Yagi antenna, which is most widely used for television receiving, has simple form and good directiyity as well as high gain, but it must be made with linear elements of half wave length. Therefore, the dimension of multi-element Yagi antenna becomes bulky and so a(ten it is inconvenient to install and handle, because of its big size. Moreover the frequency band width of the Yagi antenna is usually not broad enough to cover the total frequency range of VHF TV channels in our country. Recently, the aemand for an antenna which is not only small enough to install it easily anywhere but also assures good quality of pictures is generally increasing. In this study 2 elements o( folded dipole, which is small compared to its electrical ways length, are fixed parallel to each other with a narrow distance and the emfs induced in them are made to get together with some phase difference. This new phased array antenna has shown a relatively good unidirectivity through over the high channel VHF television frequency hand as well as the good PIB ratio which is comparable to that of multielements Yagi antenna. As a result this new antenna will be used as a VHF high channel TV receiving antenna and it may become better antighost antenna when used inside the room than other room antennas.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.7
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• pp.18-23
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• 2000

An active phased away antenna consists of many channels including radiator and active circuitary that contains low noise amplifiers and phase shifters. Each channel has different initial phase shift and gain because of inequality in active circuitary itself, interface between radiator and active circuitary, beam forming network and other antenna configurations. This is an inherent problem in active phased away antenna, therefore each channels' initial phase shifts and gains should be calibrated for obtaining the designed radiation pattern and antenna gain. In this paper, an efficient calibration method for the active phased array antenna is presented. By performing the above method, thhe antenna gain is increased more than 2.0 dB after calibrating considerably unequal 12 channels' initial phase shifts and gains.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.1 s.116
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• pp.44-52
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• 2007

In this paper, An active antenna of T-DMB was developed to equip to handhold gadgets by using LNA and a parasitic element allowing to miniature. The size of the fabricated active antenna is $80{\times}6{\times}0.4\;mm$ and FR4 is used for the substrate. The size of the proposed antenna is reduced by 38.8% at the operating frequency compared to one without a parasitic element, and a short stub. The proposed antenna shows improved performance at the measurement especially in the ratio of S/N compared with conventional monopole of 300 mm. The proposed antenna is well able to adapt into handhold gadgets for receiving T-DMB.