• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.68-73
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• 2009

This paper presents an easily modifiable structure of a serial peripheral interface (SPI) that is suitable for efficient testing of CMOS RF integrated circuits. The proposed SPI Is designed so that the address size and the accompanying software can be easily adjusted and modified according to the requirements and complexity of RF IC's under development. The hardware architecture and software algorithm to achieve the flexibility are described. The proposed SPI is fabricated in $0.13{\mu}m$ CMOS and successfully verified experimentally with a 2.7GHz fractional-N delta-sigma frequency synthesizer as a device under test.

• Journal of IKEEE
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• v.21 no.3
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• pp.256-259
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• 2017

SENT (single edge nibble transmission) is a serial communication protocol between automotive sensors and ECU (electronic control unit). SENT exploits digital waveform, so it has a simple and cheap architecture without transceiver circuits. Usually it is exploited as an embedded communication interface in the sensors. In this paper, a SENT interface was designed in Verilog HDL, fully complying with SAE J2716. It was implemented in FPGA, and verified on a test board. When it was synthesized, the gate count is about 2,500 gates in 0.18um technology.

• Journal of KIISE:Software and Applications
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• v.27 no.2
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• pp.148-156
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• 2000

The test technique for the failure caused by interaction between the customized interface and core function is necessary. We propose a component customization test technique by using the fault injection technique and the mutation test case selection technique. Our technique injects fault into where the customization failure may take place and selects the test case that differentiates the fault-injected component from the customized-component. Therefore, our test case has a good fault-detectability and can reduce the testing time by injecting a fault only into a place where the customization failure may take place in the interface.

• Proceedings of the Korean Society of Computer Information Conference
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• 2020.07a
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• pp.73-74
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• 2020

본 논문에서는 구현 장치에 연결된 다양한 인터페이스를 갖는 영상취득장치들 중에서 선택된 장치의 영상을 무선망을 통해 다수의 영상수신장치들에게 해당 영상을 전송하고, 원격으로 연결을 관리하는 영상송신시스템 디자인[1]의 하드웨어 구현 내용을 기술한다. 구현된 영상송신시스템 보드는 활용 요구 환경에 맞춰 영상취득을 위한 고정된 4개의 컴포지트 및 범용 USB 인터페이스, 무선 송수신 인터페이스, 전반적인 제어를 위한 CPU 모듈 등으로 구성된다. 원격의 영상수신장치들은 제안하는 구현된 송신시스템에 접속하여 개별채널을 확보하고 선택한 영상취득장치의 해당 영상을 직접 수신하고 해당 영상취득장치를 제어할 수 있다. 이를 위해서 연결된 다수의 외부 영상수신장치들과의 연결관리와 해당 영상취득장치의 제어 등과 같은 기능들을 제공하기 위한 하드웨어 보드를 구현하였다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.47-56
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• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.109-118
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• 2007

As the integration density and the operating speed of System on Chips (SoCs) become increasingly high, it is crucial to test delay defects on the SoCs. This paper introduces an enhanced IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller for the wrapper interface logic, and proposes a transition delay fault test method. The method proposed can detect slow-to-rise and slow-to-fall faults sequentially with low area overhead and short test time. and simultaneously test IEEE 1500 wrapped cores operating at different core clocks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.5A
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• pp.879-888
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• 2001

본 논문에서는 무선 LAN의 MAC 계층 프로토콜을 고속으로 처리하는 MAC 기능 칩을 개발하였다. 개발된 MAC 칩은 CPU와의 인터페이스를 위한 제어 레지스터들과 인터럽트 체계를 가지고 있으며, 프레임 단위로 송수신 데이터를 처리한다. 또한 PFDM 방식 물리계층 모뎀을 위한 직렬전송 인터페이스를 가지고 있다. 개발된 MAC 칩은 크게 프로토콜제어기능 블록, 송신기능 블록 및 수신기능 블록 등으로 구성되었으며, IEEE 802.11 규격에 제시된 대부분의 DCF 기능을 지원한다. 구현된 MAC 칩의 동작을 검증하기 위해 RTS-CTS 절차 기능, IFS(Inter Frame Space) 기능, 액세스 절차, 백오프 절차, 재전송 기능, 분할된(fragmented) 프레임 송수신 기능, 중복수신 프레임 검출 기능, 가상 캐리어 검출기능(NAV 기능), 수신에러 발생 경우 처리 기능, Broadcast 프레임 송수신 기능, Beacon 프레임 송수신 기능, 송수신 FIFO 동작 기능 등을 시뮬레이션을 통해 시험하였으며, 시험 결과 모두 정상적으로 동작함을 확인하였다. 본 논문을 통해 개발된 MAC 기능 칩을 이용할 경우 고속 무선 LAN 시스템의 CPU 부하(load)와 펌웨어의 크기를 크게 줄일 수 있을 것으로 기대된다.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.975-978
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• 2003

본 논문에서는 비디오 신호 인터페이스를 위해 10비트 50MHz ADC 를 설계하였으며 DCL(digital-error correction logic)을 갖는 3-3-3-4 구조의 파이프라인 방식을 사용하였다. SHA(sample and hold amplifier)와 MDAC (multiplying digital-to-analog converter)에 쓰이는 증폭기는 높은 이득을 갖도록 gain-boosting 기법을 적용하였으며, 전력소모와 면적을 줄이기 위해 capacitor scaling 기법을 적용하였다. 본 ADC 는 0.35 μm double-poly four-metal n-well CMOS 공정으로 설계 및 제작하였으며, 전체 회로는 3.3V 단일 전원 전압에서 동작하도록 설계하였다. 측정 결과 5MHz 의 입력을 인가하였을 때 SNDR 은 56.7dB, 전체 전력 소모는 112mW 이며, 입출력 단의 패드를 포함한 전체 칩 면적은 2.6mm×2.6mm이다.

• The Journal of the Korea Contents Association
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• v.1 no.1
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• pp.59-67
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• 2001

A new intelligent home appliance is being appeared with overlap of telecommunication and home appliance technology. In this kind of product the user interface especially on screen display(OSD) and remote controller, holds a key post and is critical factor of performance and usability. In spite of this importance, the user interface is designed by circurt engineer from a viewpoint of engineering on the basis of his experience and unsophisticated insight. Therefore this study clarifies a user- centered design process of OSD from the designer's viewpoint on the basis of development case and gives a guideline for each stage in consideration of characteristic features that the user interface design of OSD is highly enfluenced by hardware specification and restricted by remote controller as input device.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.5
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• pp.468-476
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• 2000

Binding the object-oriented programming language C++ with a database management system provides a persistency to C++ programming objects so that objects can persist after program termina~,on. In such a binding system, we can manage a persistent object same as that we use a transient object and also use database management facilities such as transaction management and concurrency control. This paper presents a method providing the persistency to C++ programming objects in the binding system. We propose an improved interface based on C++ binding of ODMG-97 and present the design and implementation technique of it. The proposed interface provides a seamless interface for creating objects of the persistent capable class. We can create a persistent object without its class name as we do not give a class name when creating a transient object. Also, we guarantee the type compatibilty between the obiect created in database and the obiect created in main memory.