• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.109-112
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• 2003

본 논문에서는 확장 유클리드 알고리즘을 이용하여 VLSI 구현에 적합한 GF(2/sup m/)에서의 나눗셈 알고리즘을 제안하였다. 제안하는 나눗셈 알고리즘은 GF(2/sup m/)에서 2m-2번의 반복적인 비트 연산을 필요로 하며 입력 데이터에 의존적인 하드웨어 구조를 새로운 (m+1)-bit의 유한체 G와 H를 도입하여 간단하게 제어하도록 구현하였다. 본 논문에서 제안하는 알고리즘은 유한체 곱셈과 나눗셈이 요구되는 Error Correction Code와 암호 알고리즘에 효율적으로 적용이 가능하다. 현재 대표적으로 사용되는 기존 나눗셈 알고리즘과 비교해 볼 때 연산 시간은 비슷하지만 2-bit의 제어신호만을 필요로 하기 때문에 입력 데이터에 독립적인 O(1)의 complexity를 가짐으로 O(log₂(m+1))의 컨트롤을 갖는 다른 두 알고리즘에 비해 하드웨어 리소스 면에서 월등한 결과를 보인다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.36-42
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• 2002

In this paper, we proposed a multiplicative algorithm for two polynomials with all non-zero coefficients over finite field GF($P^m$). Using the proposed multiplicative algorithm, we constructed the multiplier of modular architecture with parallel in-output. The proposed multiplier is composed of $(m+1)^2$ identical cells, each cell consists of one mod(p) additional gate and one mod(p) multiplicative gate. Proposed multiplier need one mod(p) multiplicative gate delay time and m mod(p) additional gate delay time not clock. Also, our architecture is regular and possesses the property of modularity, therefore well-suited for VLSI implementation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.23-30
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• 2008

Recently, a considerable number of studies have been conducted on pairing based cryptosystems. The efficiency of pairing based cryptosystems depends on finite fields, similar to existing public key cryptosystems. In general, pairing based ctyptosystems are defined over finite fields of chracteristic three, GF($3^m$), based on trinomials. A multiplication in GF($3^m$) is the most dominant operation. This paper proposes a new most significant digit(MSD)-first digit- serial multiplier. The proposed MSD-first digit-serial multiplier has the same area complexity compared to previous multipliers, since the modular reduction step is performed in parallel. And the critical path delay is reduced from 1MUL+(log ${\lceil}n{\rceil}$+1)ADD to 1MUL+(log ${\lceil}n+1{\rceil}$)ADD. Therefore, when the digit size is not $2^k$, the time delay is reduced by one addition.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.510-520
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• 2011

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and compose the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells that have a mod(3) addition gate and a mod(3) multiplication gate. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.40-47
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• 2006

The finite-field multiplication can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-parallel, bit-serial and systolic multipliers, the proposed multiplier has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.628-636
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• 2010

In this paper, we present a new type high speed parallel multiplier for performing the multiplication of two polynomials using standard basis in the finite fields GF($2^m$). Prior to construct the multiplier circuits, we design the basic cell of vector code generator(VCG) to perform the parallel multiplication of a multiplicand polynomial with a irreducible polynomial and design the partial product result cell(PPC) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial with VCG circuits. The presented multiplier performs high speed parallel multiplication to connect PPC with VCG. The basic cell of VCG and PPC consists of one AND gate and one XOR gate respectively. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields GF($2^4$). Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper uses the VCGs and PPCS repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSL.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.81-87
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• 1989

A cellular array multiplier for performing the multiplication of two elements in the finite field GF($2^m$) is presented in this paper. This multiplier is consisted of three operation part ; the multiplicative operation part, the modular operation part, and the primitive irreducible polynomial operation part. The multiplicative operation part and the modular operation part are composed by the basic cellular arrays designed AND gate and XOR gate. The primitive iirreducible operation part is constructed by XOR gates, D flip-flop circuits and a inverter. The multiplier presented here, is simple and regular for the wire routing and possesses the properties of concurrency and modularity. Also, it is expansible for the multiplication of two elements in the finite field increasing the degree m and suitable for VLSI implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1209-1217
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• 2008

In this paper, we present a new bit-parallel multiplier for performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the vector code generator(VCG) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of VCG have two AND gates and two XOR gates. Using these VCG, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the VCGs with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.1-10
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• 2004

A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF$(2^m)$ is presented in this paper. The presented cellular way parallel multiplier consists of three operation parts: the multiplicative operation part (MULOP), the irreducible polynomial operation part (IPOP), and the modular operation part (MODOP). The MULOP and the MODOP are composed if the basic cells which are designed with AND Bates and XOR Bates. The IPOP is constructed by XOR gates and D flip-flops. This multiplier is simulated by clock period l${\mu}\textrm{s}$ using PSpice. The proposed multiplier is designed by 24 AND gates, 32 XOR gates and 4 D flip-flops when degree m is 4. In case of using AOP irreducible polynomial, this multiplier requires 24 AND gates and XOR fates respectively. and not use D flip-flop. The operating time of MULOP in the presented multiplier requires one unit time(clock time), and the operating time of MODOP using IPOP requires m unit times(clock times). Therefore total operating time is m+1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomials in the finite fields with very large m.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.833-836
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• 2007

Nowadays, the rapid increase of the available amount of internet and system performance has revealed urgent need a method of decryption about digital encryption for stabilization of multimedia data transmission. In this paper, we propose a method of decryption of each frame about video data. Also for advanced decryption, we propose color image decryption method through 4-bit binary of $GF(2^m)$ inverse about an each frame.