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http://dx.doi.org/10.3745/KIPSTA.2004.11A.1.001

A Design of Cellular Array Parallel Multiplier on Finite Fields GF(2m)  

Seong, Hyeon-Kyeong (상지대학교 컴퓨터·정보공학부)
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The KIPS Transactions:PartA / v.11A, no.1, 2004 , pp. 1-10 More about this Journal
Abstract
A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF$(2^m)$ is presented in this paper. The presented cellular way parallel multiplier consists of three operation parts: the multiplicative operation part (MULOP), the irreducible polynomial operation part (IPOP), and the modular operation part (MODOP). The MULOP and the MODOP are composed if the basic cells which are designed with AND Bates and XOR Bates. The IPOP is constructed by XOR gates and D flip-flops. This multiplier is simulated by clock period l${\mu}\textrm{s}$ using PSpice. The proposed multiplier is designed by 24 AND gates, 32 XOR gates and 4 D flip-flops when degree m is 4. In case of using AOP irreducible polynomial, this multiplier requires 24 AND gates and XOR fates respectively. and not use D flip-flop. The operating time of MULOP in the presented multiplier requires one unit time(clock time), and the operating time of MODOP using IPOP requires m unit times(clock times). Therefore total operating time is m+1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomials in the finite fields with very large m.
Keywords
Finite fields GF$(2^m)$; Parallel Multiplier; Systolic Multiplier; Irreducible Polynomial; Reed-Solomon Decoder;
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