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Design of a systolic radix-4 finite-field multiplier for the elliptic curve cryptography  

Park Tae-Geun (School of Information, Communications and Electronics Engineering, The Catholic University of Korea)
Kim Ju-Young (School of Information, Communications and Electronics Engineering, The Catholic University of Korea)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.3, 2006 , pp. 40-47 More about this Journal
Abstract
The finite-field multiplication can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-parallel, bit-serial and systolic multipliers, the proposed multiplier has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.
Keywords
finite field multiplier; systolic; radix-4; VLSI;
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Times Cited By KSCI : 1  (Citation Analysis)
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