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Design of a Parallel Multiplier for Irreducible Polynomials with All Non-zero Coefficients over GF($p^m$)  

Park, Seung-Yong (Dept. of Computer & Information, Jaenueng Collage)
Hwang, Jong-Hak (Korea Sport Science Institute)
Kim, Heung-Soo (Dept. of Electronic Eng., Inha University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.39, no.4, 2002 , pp. 36-42 More about this Journal
Abstract
In this paper, we proposed a multiplicative algorithm for two polynomials with all non-zero coefficients over finite field GF($P^m$). Using the proposed multiplicative algorithm, we constructed the multiplier of modular architecture with parallel in-output. The proposed multiplier is composed of $(m+1)^2$ identical cells, each cell consists of one mod(p) additional gate and one mod(p) multiplicative gate. Proposed multiplier need one mod(p) multiplicative gate delay time and m mod(p) additional gate delay time not clock. Also, our architecture is regular and possesses the property of modularity, therefore well-suited for VLSI implementation.
Keywords
승산기;GF;유한체;병렬승산기;다치논리;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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