• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.974-984
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• 2000

A CMOS voltage driver circuit for voltage down converter is proposed. An adaptive biasing technique is used to enhance load regulation characteristics. The proposed driver circuit uses the NMOS transistor as a driving transistor, so it does not suffer from large Miller capacitances which is one of the problems with conventional PMOS driving transistor, and hence achieves good phase margin and stable frequency response. No additional complex circuit for frequency compensation such as compensation capacitor is required in this implementation. For the same current capability, the size of NMOS transistor in driver circuit is smaller than that of PMOS counterpart. So the smaller die area can be achieved. The circuits is implemented using a 0.8 ${\mu}{\textrm}{m}$ CMOS process and has a die area of 150 ${\mu}{\textrm}{m}$ x 360 ${\mu}{\textrm}{m}$. Proposed circuit has a quiescent power of 60 . In the current driving range from 100 $mutextrm{A}$ to 50 ㎃, load regulation of 5.6 ㎷ is measured.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.44 no.6
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• pp.492-501
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• 2016

Three-Loop autopilot is generally used for the acceleration control of guided missiles. Because the acceleration command to the three-loop autopilot is given as values at the center of gravity, feedback information of IMU should be obtained at the same position. However, the position of IMU might not be located at the center of gravity due to the sub-system assignment. This paper presents the stability analysis of three-loop autopilot with respect to the arbitrary position of IMU and variation rate of center of gravity. Gain and phase margins are calculated for several trim points for general anti-tank missiles.

• Journal of the Korean Society of Propulsion Engineers
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• v.22 no.3
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• pp.46-52
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• 2018

A simple Crocco's $n-{\tau}$ time delay model and linear analysis of fluid flow coupled with acoustics are combined to investigate the high frequency combustion instability in the combustion chamber of LOX/hydrocarbon engines. The partial differential equation of the velocity potential is separated into ordinary differential equations, and eigenvalues that correspond to tangential resonance modes in the cylindrical chamber are determined. A general solution is obtained by solving the differential equation in the axial direction, and boundary conditions at the injector face and nozzle entrance are applied in order to calculate the chamber admittance. Frequency analysis of the transfer function is used to evaluate the stability of system. Stability margin is determined from the system gain and phase angle for the desired frequency range of 1T mode. The chamber model with variable baffle length and configurations are also considered in order to enhance the 1T mode stability of the combustion chamber.

• Journal of IKEEE
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• v.14 no.2
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• pp.90-97
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• 2010

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device and DTMOS Error Amplifier is presented in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS(DT-CMOS) with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an DT-CMOS error amplifier and a comparator circuit as a block. the proposed DT-CMOS Error Amplifier has 72dB DC gain and 83.5deg phase margin. also Error Amplifier that use DTMOS more than CMOS showed power consumption decrease of about 30%. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device is achieved the high efficiency near 96% at 100mA output current. And DC-DC converter is designed with Low Drop Out regulator(LDO regulator) in stand-by mode which fewer than 1mA for high efficiency.

• Aerospace Engineering and Technology
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• v.1 no.2
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• pp.105-112
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• 2002

In this paper, a servo filter design for the gimbal engine actuator system of KSR-III(Korea Sounding Rocket-III) is considered. A reasonable filter structure is determined based on the actuator analytic models. The servo filter consists of a 2-nd order lowpass filter and a 1-st order compensator. The lowpass filter is required to protect the actuator from high frequency vibration, and the compensator to enhance the resulting stability. A Butterworth type servo filter is considered as the simplest one. The final servo filter type is determined by evaluating simultaneously both high frequency gain reduction performance and the corresponding KSR-III stability margin. Consequently it is revealed that a notch type servo filter located on the error between command signal and feedback signal in the control loop is very effective. Later, based on the proposed servo filter type, an onboard servo filter hardware of KSR-III will be designed and tested.

• Journal of IKEEE
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• v.12 no.3
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• pp.176-183
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• 2008

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device is proposed in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit as a block. The Saw-tooth generator is made to have 1.2 MHz oscillation frequency and full range of output swing from ground to supply voltage(VDD:3.3V). The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device, achieved the high efficiency near 95% at 100mA output current. And DC-DC converter is designed with LDO in stand-by mode which fewer than 1mA for high efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of IKEEE
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• v.13 no.4
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• pp.63-68
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• 2009

The power management integrated circuit(PMIC) for CCD image sensor is presented in this study. A CCD image sensor is very sensitive against temperature. The temperature, that is heat, is generally generated by the PMIC with low efficiency. Since the generated heat influences performance of CCD image sensor, it should be minimized by using a PMIC which has a high efficiency. In order to develop the PMIC with high efficiency, the input stage is designed with synchronous type step down DC-DC converter. The operating range of the converter is from 5V to 15V and the converter is controlled using PWM method. The PWM control circuit consists of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit. The saw-tooth generator is designed with 1.2MHz oscillation frequency. The comparator is designed with the two stages OP Amp. And the error amplifier has 40dB DC gain and $77^{\circ}$ phase margin. The output of the step down converter is connected to input stage of the charge pump. The output of the charge pump is connected to input of the LDO which is the output stage of the PMIC. Finally, the PMIC, based on the PWM control circuit and the charge pump and the LDO, has output voltage of 15V, -7.5V, 3.3V and 5V. The PMIC is designed with a 0.35um process.

• Progress in Medical Physics
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• v.25 no.4
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• pp.242-247
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• 2014

To see the discrepancies between the calculated and the delivered dose distribution of IMRT fields for respiratory-induced moving target according to the motion ranges. Four IMRT plans in which there are five fields, for lung and liver patients were selected. The gantry angles were set to $0^{\circ}$ for every field and recalculated using TPS (Eclipse Ver 8.1, Varian Medical Systems, Inc., USA). The ion-chamber array detector (MatriXX, IBA Dosimetry, Germany) was placed on the respiratory simulating platform and made it to move with ranges of 1, 2, and 3 cm, respectively. The IMRT fields were delivered to the detector with 30~70% gating windows. The comparison was performed by gamma index with tolerance of 3 mm and 3%. The average pass rate was 98.63% when there's no motion. When 1.0, 2.0, 3.0 cm motion ranges were simulated, the average pass rate were 98.59%, 97.82%, and 95.84%, respectively. Therefore, ITV margin should be increased or gating windows should be decreased for targets with large motion ranges.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.