• The Journal of the Acoustical Society of Korea
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• v.35 no.5
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• pp.368-374
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• 2016

This paper presents constructing transmitter and receiver by using a direct sequence spread spectrum techniques to DPSK (Differential Phase-Shift Keying) scheme in underwater acoustic communication. Since DPSK signal can be demodulated if the receiver knows only the phase difference between the adjacent bits, DPSK receiver structure has the advantage of being simplified. In the conventional receiver, two adjacent symbols of transmitted signal before despread are passed to the transition correlator that detects data by comparing maximum correlation outputs. At this time, the error for maximum value of the correlator output may increase because of low SNR (Signal to Noise Ratio) or high Doppler shift frequency according to the underwater channel. In this paper, we propose a method for accurate detection result using the width as well as the magnitude among outputs produced by the correlator. The performances of the proposed method was evaluated by simulation and lake trial data.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.478-479
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• 2018

본 논문에서는 무정전 CTTS 시스템에 적합한 영전력 투입과 영전류 차단이 가능한 알고리즘을 제안한다. 제안된 알고리즘은 이종전원에 크기와 위상차를 고정도로 검출하기 위해 이종전원의 차를 검출하였고 이를 통해 CTTS 투입 시 돌입전류를 감소시킬 수 있었다. 또한 순시 유무효전력 제어로 CTTS 차단 시 UPS 출력전류를 영전류로 제어하여 무아크 및 계통 안정화를 이룰 수 있었다. 또한 본 시스템은 UPS 동작뿐만 아니라 무효전력 보상기인 조상기로 사용 가능하며 특히 계통 전압안정화용으로 사용가능함을 확인하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.99-105
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• 2014

A reference spur suppressed PLL with two-symmetrical loops without changing the bandwidth which is optimized to suppress phase noise and reduce locking time has been designed. The principle of suppressing a reference signal spur is to stabilize the input voltage of voltage controlled oscillator (VCO). The proposed PLL consists of a phase-frequency detector(PFD) which has two outputs, two charge pumps(CP), two loop filters(LF), a divider and a VCO which has two inputs. Simulation results with $0.18{\mu}m$ CMOS process show that the reference spur is approximately suppressed to 1/2 of the reference spur in a conventional PLL. Even though there is a 5% process variation in the magnitude of R and C, the simulation result shows that the reference spur is still suppressed to 1/2 of the reference spur in a conventional PLL. The power consumption is 6.3mW at the power supply of 1.8V.

• Proceedings of the KIEE Conference
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• 2008.10c
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• pp.35-37
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• 2008

본 논문은 IPM 설계 시 인덕턴스 용량을 산정하는 방법과, 모터와 드라이브의 턴 폴트와 상 개방에 의한 고장 시 검출할 수 있는 방법을 제안하였다. IPM의 인덕턴스 용량 산정은 모터의 전압과 전압, 전류의 위상차를 이용하여 선정 하는 방법을 제시하였다. 고장 검출과 관련해서는 가장 일반적으로 많이 발생하는 코일 단락과 개방에 의한 전류의 왜곡 현상을 보기위한 실험 환경을 구성하였으며, 실험 걸과를 흥하여 전류 왜곡에 의한 고장 검출의 가능성을 제시하였다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.62-67
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• 1999

Phase rotational is a practical problem in the implementation of coherent demodulation. Large phase noise may intorduce phase rotation in the demodulator which results in repeated decision errors. This paper presents a simple and yet very efficient technique in building a carrier recovery loop which minimizes the phase rotation by improving the stability of the decision-directed carrier recovery loop. Simulation shows this novel technique improves the performance of the carrier recovery loop as well as stability.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.707-714
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• 2010

Since an LFSR(linear feedback shift register) as a pattern generator has solely linear dependency in itself, it generates sequences by moving the bit positions for pattern generation. So the correlation between the generated patterns is high and thus reduces the possibility of fault detection. To overcome these problems many researchers studied to have goodness of randomness between the output test patterns. In this paper, we propose the new and effective method to construct phase shifter as PRPG(pseudo random pattern generator).

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.4
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• pp.59-64
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• 2007

In this paper, we propose a new decoding method for differentially biorthogonal chirp spread spectrum (DBO-CSS). In DBO-CSS, the information is carried on the differential phase not between the adjacent sub-chirp symbols but between the sub-chirp symbols in the same position of adjacent full-chirp symbol. So, the conventional multiple symbol differential detection (MSDD) algorithms to enhance the BER performance can not be applied to the DBO-CSS directly. In this paper, we propose a new differential detection algorithm based on a partial MSD(multiple symbol detection) and a viterbi algorithm. It is shown that the performance gain of the proposed algorithm when compared with that of the conventional detection algorithm is around 2.5dB at BER = 10-5.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.403-408
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• 2002

In this paper, the performance on the PN code acquisition of DS/CDMA system was analyzed using the Nakagami-m probability density function considered fading environment. The equations on detection probability, $P_D$ and false alarm probability, ($P_{FA}$, decision variables affecting the PN code acquisition time were derived and proved using simulation in order to analyze the performance. In conclusion, It was necessary increasing the gain of PLL for correcting phase errors and improving the acquisition performance of PN code in apply to the rake receiver.

• Journal of the Korean Solar Energy Society
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• v.27 no.2
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• pp.37-44
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• 2007

As photovoltaic(PV) power generation system becomes more common, it will be necessary to investigate islanding detection method for PV systems. Islanding of PV systems can cause a variety of problems and must be prevented. However, if the real and reactive power of the load and PV system are closely matched, islanding detection by Passive methods becomes difficult. Also, most active methods lose effectiveness when there are several PV systems feeding the same island. The active frequency drift positive feedback method(AFDPF) enables islanding detection by forcing the frequency of the voltage in the island to drift up or down. In this paper the research for the minimum value of chopping fraction gain applied digital phase-locked-loop (DPLL) to AFDPF considering output power quality and islanding prevention performance are performed by simulation and experiment according to IEEE Std 929-2000 islanding test.

• 전자공학회논문지 IE
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• v.46 no.1
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• pp.1-6
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• 2009

This paper presents the digital PLL architecture and design for improving the frequency detection range and locking time for wide-band frequency synthesizer applications. In this research, a wide-range digital logic quadricorrelator is used for wide-band and fast frequency detector and sigma-delta modulator with 2-bit up-down counter is adopted for DCO control. The proposed digital PLL reduces the phase noise from quantization effect and is suitable for implementation of wide-band fast-locking as well as low power features, which is in high demand for mobile multimedia applications.