• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.176-179
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• 2000

The PLL synthesizer is used often in communication system due to several merits, such as broad bandwidth, high accuracy and stability of frequency. But it is difficult to use in current digital communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed frequency synthesizer that generate the clock frequency randomly at a high speed using the DDS technology and is applied to the pattern generator systemfor for digital image.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.443-447
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• 2001

The PLL synthesizer is used often in communication system due to several merits, such as broad bandwidth, high accuracy and stability of frequency. But it is difficult to use in torrent digital communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed frequency synthesizer that generate the clock frequency randomly at a high speed using the DDS technology and is applied to the pattern generator system for digital image.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.2
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• pp.134-141
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• 2009

The new method is proposed to improve the dynamics of the phase angle detector during abrupt voltage dip caused by a grid fault. Usually, LPF(low pass filter) is used in the feedback loop of SRF(Synchronous Reference Frame) - PLL (Phase Locked Loop) system because the measured grid voltage contains harmonic distortions and sensor noises. A better transient response can be obtained with the proposed design method for SRF-PLL by the analysis of linearized model of the PLL system including LPF. Furthermore, in the proposed method, the controller gain and LPF cut-off frequency are changed from normal value to transient value when the voltage disturbance is detected. This paper shows the feasibility and the usefulness of the proposed methods through the computer simulation and the experiment.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.1
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• pp.43-51
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• 2010

This paper proposes an analysis of voltage delay and compensation for current control in H-Bridge Multi-Level (HBML) inverters for a medium voltage motor drive with vector control. It is shown that the expansion and modularization capability of the HBML inverter is improved in case of using Phase-Shifted Pulse Width Modulation (PSPWM) since individual inverter modules operate more independently. But, the PSPWM of HBML has a phase difference between reference voltage and real voltage, which can cause instability in the current regulator at high speed where the ratio of the sampling frequency to the output frequency is insufficient. This instability of the current regulator is removed by adding a proposed method which compensate a phase difference between reference voltage and real voltage. The proposed method is suitable for HBML inverter controlled by PSPWM with low switching frequency and high speed motor drive. The validity of the proposed method is verified experimentally on 6,600[V] 1,400[kW] induction motor fed by an 13-level HBML inverter.

• Korean Journal of Optics and Photonics
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• v.16 no.4
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• pp.392-396
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• 2005

A new structure of tunable wavelength converter based on XCM in SOA was tried and analyzed. This converter used single SOA and had very simple structure. In this paper, results were experimentally obtained and demonstrated. Pump signal was generated with NRZ $(PRBS\;2^{31}-1)$ and data rate 2.5 Gbps. WDM multi conveted signals showed more than 8.3 dB extinction ratio. For BER performance, all these converted signals had within 5.0 dB power penalty compared with the pump signal. With these results, we showed that this converter was suitable for 2.5 Gbps WDM multi-channel wavelength converting.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.602-612
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• 2013

In this paper, a design and fabrication of miniaturized 5.3 GHz reflection type $360^{\circ}$ analog phase shifter with branch line coupler and $360^{\circ}$ variable reactance load. In order to miniaturize phase shifter, novel branch line coupler is proposed. The novel branch line coupler is miniaturized using transformation of transmission line to T and ${\pi}$ type equivalent circuit. The miniaturized branch line coupler has small size of above 50 % compared with conventional branch line coupler. For wide phase shift range, $360^{\circ}$ variable reactance load structure is adopted. Especially, the structure was improved for linear phase shift by adding transmission line which acts as an impedance transformer. The improved structure was miniaturized using the equivalent lumped-element of transmission line. The fabricated phase shifter with $15{\times}15mm^2$ shows wide phase shift of above $480^{\circ}$, the insertion loss of -4~-6 dB and the reflection loss of below -20 dB at 5.3 GHz under 0~10 V control voltage range.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.2
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• pp.124-132
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• 1987

In this paper, a new Open and Closed Loop Alternation(OCLA) frequency synthesizer is developed to eliminate a frequency error occurring in the transition state of a frequency hopping. This frequency synthesizer consists of a phase comparator(PC), two low pass filters(LPF), two voltage controlled oscillators(VCO), switching elements, a programmable divider and frequency hopping controller, and the stabilized output frequency can be obtained by switching performance. In addigion, it can be found that the characteristic of its circuit construction makes it easy to attach an external circuitry to the open loop.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.1
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• pp.22-27
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• 2001

본 논문에서는 복잡한 하이퍼카오스 신호를 발생시키는 HVPM (Hyperchaotic Volume Preserving Maps) 모델의 회로를 제안하고, 보드상에서 구현하고자 한다. 제안한 HVPM 모델은 3차원 이산시간(discrete-time) 연립차분방정식으로 구성되어 있으며, 비선형 사상(maps)과 모듈러(modulus) 함수를 사용하여 랜덤한 카오스 어트랙터(attractor)를 발생시킨다. 이러한 HVPM 모델을 하드웨로 구현하기 위하여 연산 부분은 연산증폭기를 사용하고, 매핑(mapping) 부분은 N형 함수와 비교기를 사용하여 설계한다. 특히, N형의 비선형 함수는 CMOS 전달특성과 선형증폭기의 출력특성을 조합하여 독특하게 구현하였다. 구현한 보드상의 실험에서 카오스 시스템 파라미터 값에 대응하는 가변저항기를 조절하여 비주기적인 하이퍼카오스 신호를 발생시킴을 입증하였다. 또한 출력된 카오스 신호들간의 오실로스코프 사진에서 위상공간(phase space)의 동적응답은 랜덤한 어트랙터를 발생시킴을 확인할 수 있었다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.177-182
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• 2007

This paper presents the InGaP/GaAs HBT differential LC VCO with low phase noise performance for adaptive feedback interference cancellation system(AF-lCS). The VCO is verified with enhanced tank structure including filtering technique. The output tuning range for proposed VCO using asymmetric inductor and symmetric capacitors withlow pass filtering technique is 207 MHz. The output powers are -6.68 including balun and cable loss. The phase noise of this VCO at 10 kHz, 100 kHz and 1 MHz are -102.02 dBc/Hz, -112.04 dBc/Hz and -130.40 dBc/Hz. The VCO is designed within total size of $0.9{\times}0.9mm^2$.