• Proceedings of the KSME Conference
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• 2005.11a
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• pp.133.2-133.2
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• 2005

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1983.04a
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• pp.29-32
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• 1983

In order to design the simple and economic Band-Pass Active filter, 2nd-order BPF using OP-amplifier were studied by their experments.

• Journal of the KSME
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• v.25 no.2
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• pp.130-136
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• 1985

확정적 계측신호에 극한시키며 현장 혹은 연구실에 종사하고 있는 기계기술자에게 필요로 하는 애널로그계측과 디지틀계측의 특성과 계측시스템의 구성, 연산증폭기(Op. Amp)의 원리 및 응용, 측정신호의 선형화, 마이크로 프로세서의 원리 A/D, D/A 변환기의 원리 및 응용, 자료처리시 스템, 센서의 원리 및 응용, 디지틀계측시스템의 최근동향등 메카트로닉스시대에서 요청되는 계 측공학의 주요과제에 대하여 기술한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.51-57
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• 2015

In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1987.10a
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• pp.236-238
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• 1987

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.565-570
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• 2012

This paper has proposed a multi-channel low pass filter (LPF) for LTE-Advanced systems. The proposed LPF is an active-RC 5th chebyshev topology with three cut-off frequencies of 5 MHz, 10 MHz, and 40 MHz. A 3-bit tuning circuit has been adopted to prevent variations of each cut-off frequency from process, voltage, and temperature (PVT). To achieve a high cut-off frequency of 40 MHz, an operational amplifier used in the proposed filter has employed a PMOS cross-connection load with a negative impedance. A proposed filter has been implemented in a 0.13-${\mu}m$ CMOS technology and consumes 20.2 mW with a 1.2 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.29-36
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• 2000

The principle and design of two-stage CMOS operational amplifier with rail-to-rail input and class-AB output stage is presented. The rail-to-rail input stage shows almost constant transconductance independent of the common mode input voltage range in global transistor operation region. This new technique does not make use of accurate current-voltage relationship of MOS transistors. Hence it was achieved by using simple linear relationship of currents. The simulated transconductance variation using SPICE is less the 4.3%. The proposed global two-stage opamp can operate both in strong inversion and in weak inversion. Class AB output stage proposed also has a full output voltage swing and a well-defined quiescent current that does not depend on power supply voltage. Since feedback class- AB control is used, it is expected that this output stage can be operating in extremely low voltage. The variation of DC-gain and unity-gain frequency is each 4.2% and 12%, respectively.

• Journal of IKEEE
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• v.19 no.1
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• pp.87-93
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• 2015

In this paper, a $145{\mu}W$, 87dB SNR, Low power 3rd order Sigma-Delta Modulator with Op-amp sharing is proposed. Conventional architecture with analog path and digital path is improved by adding a delayed feed -forward path for disadvantages that coefficient value of the first integrator is small. Proposed architecture has a larger coefficient value of the first integrator to remove the digital path. Power consumption of proposed architecture using op-amp sharing is lower than conventional architecture. Simulation results for the proposed SDM designed in $0.18{\mu}m$ CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and sampling frequency 2.8224MHz shows SNR(Signal to Noise Ratio) of 87dB, the power consumption of $145{\mu}W$.

• Journal of Convergence for Information Technology
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• v.11 no.8
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• pp.1-7
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• 2021

In this paper, a method of extending 1 bit by adding an external device to a parallel interface type Digital-to-Analog conversion(D/A C) circuit is presented. To do this, the principle of the D/A C circuit was examined, and the problems that occur when extending one bit by adding individual devices were analyzed, and a bit extension method of the D/A devices using an OP-Amp. circuit was presented. As the proposed method uses the high-precision characteristics of the OP-Amp., even if an error occurs in the device, only the overall size of the output waveform is affected, and the voltage reversal phenomenon that occurs between each bit does not occur. In order to confirm the effect of the proposed method, an experimental circuit was constructed and the absolute voltage of the output and the relative error were measured. As a result, a voltage error of 0.0756% appeared, confirming that the 0.195% requirement for one bit expansion by adding individual devices was sufficiently satisfied.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2000.11a
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• pp.263-266
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• 2000

본 논문에서는 복잡한 카오스 신호를 발생시키는 HVPM(hyperchaotic volume preserving maps) 모델과 HVPM 모델의 구현회로를 제안한다. 랜덤한 카오스 신호를 발생시키기 위하여 3차원 이산시간(discrete-time) 연산과 비선형 사상(maps)으로 모듈러(modulus) 함수를 이용하여 하이퍼카오스 신호를 발생시킨다. 그리고 HVPM 모델은 여러 가지 시스템 파라미터들을 변화시키면 다양한 카오스 신호를 발생시킬 수 있으며, 출력되는 카오스 신호는 비주기성을 갖게 된다. 이러한 특징을 갖는 HVPM 모델의 회로 구현을 위하여 2단 N형의 함수를 CMOS와 선형 연산증폭기 및 비교기를 이용하여 보드상에서 구현하여, 다양한 하이퍼카오스 신호를 확인할 수 있었다.