• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.4
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• pp.364-375
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• 2014

Parametric array transducers are used for long-range and highly directional communication in an underwater environments. The power amplifiers for parametric array transducers should have sufficient linear output characteristic and high efficiency to avoid communication errors, system heating, and fuel problems. But the conventional power amplifier with fixed source voltage is very low efficient due to large power loss by the big difference between the fixed source voltage and the amplifier output voltage. Thus to solve the problems this paper proposes the high efficiency power amplifier for parametric array transducers. The proposed power amplifier ensures high linearity of output characteristic by utilizing the push-pull class B type amplifier and furthermore gets high efficiency by applying the envelope tracking technique that variable source voltage tracks the envelope of the amplified signal. Also the paper suggests the detailed circuit topology and design guideline of class B push-pull type amplifier and variable output voltage AC/DC converter. Its characteristics are verified by the detailed simulation and experimental results.

• Journal of Broadcast Engineering
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• v.24 no.4
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• pp.660-669
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• 2019

Recently, with the development of three-dimensional scanning devices and multi-dimensional array cameras, research is continuously conducted on techniques for handling three-dimensional data in application fields such as AR (Augmented Reality) / VR (Virtual Reality) and autonomous traveling. In particular, in the AR / VR field, content that expresses 3D video as point data has appeared, but this requires a larger amount of data than conventional 2D images. Therefore, in order to serve 3D point cloud content to users, various technological developments such as highly efficient encoding / decoding and storage, transfer, etc. are required. In this paper, V-PCC bit stream created using V-PCC encoder proposed in MPEG-I (MPEG-Immersive) V-PCC (Video based Point Cloud Compression) group, It is defined by the MPEG-DASH (Dynamic Adaptive Streaming over HTTP) standard, and provides to be composed of segments. Also, in order to provide the user with the information of the 3D coordinate system, the depth information parameter of the signaling message is additionally defined. Then, we design a verification platform to verify the technology proposed in this paper, and confirm it in terms of the algorithm of the proposed technology.

• The Journal of the Acoustical Society of Korea
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• v.38 no.2
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• pp.145-153
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• 2019

Adaptive beamforming methods are known to suppress sidelobes and improve detection performance of weak signal by constructing weight vectors depending on the received signal itself. A standard adaptive beamforming like the MVDR (Minimum Variance Distortionless Response) is very sensitive to mismatches between weight vectors and actual signal steering vectors. Also, a large computational complexity for estimating a stable covariance matrix is required when wideband beamforming for a large-scale array is used. In this paper, we exploit the WBRCB (Wideband Robust Capon Beamforming) method for stable and robust wideband adaptive beamforming of a passive large uniform line array sonar. To improve robustness of adaptive beamforming performance in the presence of mismatches, we extract a optimum mismatch parameter. WBRCB with extracted mismatch parameter shows performance improvement in beamforming using synthetic and experimental passive sonar signals.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.7
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• pp.879-884
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• 2020

In the conventional video file system, videos are stored in a high performance server which has mass storage hard disks or disk arrays. For 3D internet broadcasting, real time operations are required to transmit video files to many clients. This paper describes the design of the 3D internet broadcasting system which can provide realtime streaming service to many users in the 5G environment. In reality, unicast is used to transmit multimedia contents over the internet rather than IP multicast since IP multicast has its own drawbacks in deployment, security, maintenance and so on. In addition, multimedia broadcasting service system like VoD has difficulties in applying to 3D internet broadcasting system since it requires a large amount of system and network resources. In this work, we develop a 3D internet broadcasting system which can construct effective data delivery by minimizing performance-degrading factors.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5452-5457
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• 2012

It is saving material cost and construction cost by replacing conventional building materials, and It has advantages for aesthetic value. In the Europe, the United States, Japan and other country research about BIPV is actively being carried out and marketability is also being infinity expanding. Arch type PV systems efficiency characteristics is different depending on PV array's directly connection, parallel connection and arches angle, but is a lack of analysis on this nowadays. When the arch type PV system design up, they consider about aesthetic value and they didn't consider about generation efficiency. In this paper, we try to improve the efficiency through optimization of arch type PV system and estimation of the efficiency parameters of the arch type PV system, such as latitude, longitude, temperature, insolation, arch angle and each kind loss from system organization. For improving Arched PV system efficiency, proposed multiple control inverter system, and using simulation tool of Arched PV system "Solar pro", flat-plate type and many arch type PV system configuration the driving characteristics were compared and analyzed.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.22-26
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• 2012

This paper introduces a 2.5-Gb/s optical receiver implemented in a standard 1P4M 0.18um CMOS technology for the applications of active optical HDMI cables. The optical receiver consists of a differential transimpedance amplifier(TIA), a five-stage differential limiting amplifier(LA), and an output buffer. The TIA exploits the inverter input configuration with a resistive feedback for low noise and power consumption. It is cascaded by an additional differential amplifier and a DC-balanced buffer to facilitate the following LA design. The LA consists of five gain cells, an output buffer, and an offset cancellation circuit. The proposed optical receiver demonstrates $91dB{\Omega}$ transimpedance gain, 1.55 GHz bandwidth even with the large photodiode capacitance of 320 fF, 16 pA/sqrt(Hz) average noise current spectral density within the bandwidth (corresponding to the optical sensitivity of -21.6 dBm for $10^{-12}$ BER), and 40 mW power dissipation from a single 1.8-V supply. Test chips occupy the area of $1.35{\times}2.46mm^2$ including pads. The optically measured eye-diagrams confirms wide and clear eye-openings for 2.5-Gb/s operations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.115-122
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• 2014

In this paper, reliability is secured by sensing a post-program resistance of several tens of kilo ohms and restricting a read current flowing over an unblown eFuse within $100{\mu}A$ since RWL driver and BL pull-up load circuits using a regulated voltage of V2V ($=2V{\pm}10%$) are proposed to have a wide operating voltage range for eFuse OTP memory. Also, when a comparison of a cell array of 1 row ${\times}$ 32 columns with that of 4 rows ${\times}$ 8 columns is done, the layout size of 4 rows ${\times}$ 8 columns is smaller with $187.065{\mu}m{\times}94.525{\mu}m$ ($=0.01768mm^2$) than that of 1 row ${\times}$ 32 columns with $735.96{\mu}m{\times}61.605{\mu}m$ ($=0.04534mm^2$).

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.138-143
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• 2016

The designed and fabricated millimeter-wave security screening system receives radiation energy from an object and a human body. The imaging system consist of sixteen array antennas, sixteen four-stage LNAs, sixteen detectors, an infrared camera, a CCD camera, reflector, and a focusing lens. This system requires high sensitivity and wide bandwidth to detect the input thermal noise. The LNA module of the system has been measured to have 65.8 dB in average linear gain and 82 GHz~102 GHz in bandwidth to enhance the sensitivity for thermal noise, and to receive it over a wide bandwidth. The detector is used for direct current (DC) output translation of millimeter-wave signals with a zero bias Schottky diode. The lens and front-end of the millimeter-wave sensor are important in the system to detect the input thermal noise signal. The frequency range in the receiving sensitivity of the detectors was 350 to 400 mV/mW at 0 dBm (1 mW) input power. The developed W-band imaging system is effective for detecting and identifying concealed objects such as metal or plastic.