Design of eFuse OTP Memory with Wide Operating Voltage Range for PMICs |
Jeong, Woo-Young
(Department of Electronic Engineering, Changwon National University)
Hao, Wen-Chao (Department of Electronic Engineering, Changwon National University) Ha, Pan-Bong (Department of Electronic Engineering, Changwon National University) Kim, Young-Hee (Department of Electronic Engineering, Changwon National University) |
1 | S. H. Kulkarni et al., "A 4kb metal-fuse OTP-ROM macro featuring a 2V programmable 1.37 1T1R bit cell in 32nm high-k metal-gate CMOS," IEEE Solid-State Circuits, vol. 45, no. 4, pp. 863-868, April 2010. DOI ScienceOn |
2 | J. Safran, A. Leslie, et al., "A compact eFuse programmable array memory for SOI CMOS," Symposium on VLSI Circuits, pp. 72-73, June 2007. |
3 | N. Robson et al., "Electrically programmable fuse (eFuse): From memory redundancy to autonomic chip," Proceedings of Custom Integrated Circuits Conference, pp. 799-804, Sep. 2007. |
4 | K. I. Kim et al., "Design of 256-Bit Single-Poly MTP Memory Based on the BCD Process", Journal of Central South University, pp.3460-3467, Dec. 2012. |
5 | J. H. Kim et al., "Design of 1-Kb eFuse OTP Memory IP with Reliability Considered", JSTS, pp.88-94, June 2010. |
6 | Y. H. Yang et al, "Design of High-Reliability eFuse OTP Memory for PMICs," J. Korea Inst. Inf. Commun. Eng., pp. 1455-1462, July 2012. 과학기술학회마을 DOI ScienceOn |