Journal of KIISE:Computer Systems and Theory (한국정보과학회논문지:시스템및이론)

Korean Institute of Information Scientists and Engineers (한국정보과학회)
권호 표지

A Novel Arithmetic Unit Over GF(2$^{m}$) for Reconfigurable Hardware Implementation of the Elliptic Curve Cryptographic Processor

타원곡선 암호프로세서의 재구성형 하드웨어 구현을 위한 GF(2$^{m}$)상의 새로운 연산기

  • Published : 2004.08.01
Download PDF
⟨ Previous Next ⟩

Abstract

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

Keywords

References

  1. IEEE P1363, Standard Specifications for Publickey Cryptography, 2000
  2. I. F. Blake, G. Seroussi, and N. P. Smart, Elliptic Curves in Cryptography, Cambridge University Press, 1999
  3. M. Rosing, Implementing Elliptic Curve Cryptography, Manning, 1999
  4. D. Hankerson, J. L. Hernandez, and A. Menezes, 'Implementation of Elliptic Curve Cryptography Over Binary Fields,' CHES 2000, LNCS 1965, Springer-Verlag, 2000
  5. D. Bailey and C. Paar, 'Efficient Arithmetic in Finite Field Extensions with Application in Elliptic Curve Cryptography, vol. 14, no.3, pp. 153-176, 2001 https://doi.org/10.1007/s001450010012
  6. L. Gao, S. Shrivastava and G. E. Solbelman, 'Elliptic Curve Scalar Multiplier Design Using FPGAs,' CHES 2000, LNCS 1717, Springer-Verlag, 1999
  7. G. Orlando and C. Parr, 'A High Performance Reconfigurable Elliptic Curve Processor for GF($2^m$),' CHES 2000, LNCS 1965, Springer-Verlag, 2000
  8. M. Bednara, M. Daldrup, J. von zur Gathen, J. Shokrollahi, and J. Teich, 'Reconfigurable Implementation of Elliptic Curve Crypto Algorithms,' Proc. of the International Parallel and Distributed Processing Symposium (IPDPS02), pp. 157-164, 2002
  9. J.R. Goodman, Energy Scalable Reconfigurable Cryptographic Hardware for Portable Applications,' PhD thesis, MIT, 2000
  10. G. B. Agnew, R. C. Mullin, and S. A. Vanstone, 'An Implementation for Elliptic Curve Cryptosystems Over $F_{2^{155}}$,' IEEE J. Selected Areas in Comm., vol.11, no. 5, pp. 804-813, June 1993 https://doi.org/10.1109/49.223883
  11. T. Blum and C. Paar, 'High Radix Montgomery Modular Exponentiation on Reconfigurable Hardware,' IEEE Trans. Computers., vol. 50, no. 7, pp.759-764, July 2001 https://doi.org/10.1109/12.936241
  12. K. Compton and S. Hauck, 'Reconfigurable Computing: A Survey of Systems and Software,' ACM Computing Surveys, vol. 34, no. 2, pp. 171-210, June 2002 https://doi.org/10.1145/508352.508353
  13. R. Tessier amd W. Burleson, 'Reconfigurable Computing for Digital Signal Processing: A Survey,' J. VLSI Signal Processing, vol. 28, no. 1, pp. 7-27, May 1998 https://doi.org/10.1023/A:1008155020711
  14. S.D. Han, C.H. Kim, and C. P. Hong, 'Characteristic Analysis of Modular Multiplier for GF($2^m$),' Proc. of IEEK Summer Conference 2002, vol. 25, no. 1, pp. 277-280, 2002
  15. C.-L. Wang and J.-L. Lin, 'A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF($2^m$),' IEEE Trans. Computers., vol. 42, no. 9, pp. 1141-1146, sep. 1993 https://doi.org/10.1109/12.241603
  16. M.A. Hasan and V.K. Bhargava, 'Bit-Level Systolic Divider and Multiplier for Finite Fields GF($2^m$),' IEEE Trans. Computers, vol. 41, no. 8, pp. 972-980, 1992 https://doi.org/10.1109/12.156540
  17. S.-W. Wei, 'VLSI Architectures for Computing exponentiations, Multiplicative Inverses, and Divisions in GF($2^m$),' IEEE Trans. Circuits Syst. II, vol. 44, no. 10, pp. 847-855, Oct. 1997 https://doi.org/10.1109/82.633444
  18. A.V. Dinh, R.J. Bolton, R. Mason, 'A Low Latency Architecture for Computing Multiplicative Inverses and Divisions in GF($2^m$),' IEEE Trans. Circuits Syst. II, vol. 48, no. 8, pp. 789-793, Aug. 2001 https://doi.org/10.1109/82.959871
  19. H. Brunner, A. Curiger and M. Hofstetter, 'On Computing Multiplicative Inverses in GF($2^m$),' IEEE Trans. Computers., vol. 42, no. 8, pp. 1010-1015, Aug. 1993 https://doi.org/10.1109/12.238496
  20. J.-H. Guo and C.-L. Wang, 'Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF($2^m$),' IEEE Trans. Computers., vol. 47, no. 10, pp. 1161-1167, Oct. 1998 https://doi.org/10.1109/12.729800
  21. S.K. Jain, L. Song, and K.K. Parhi, 'Efficient Semi-Systolic Architectures for Finite Field Arithmetic,' IEEE Trans. VLSI Syst., vol. 6, no. 1, pp. 101-113, Mar. 1998 https://doi.org/10.1109/92.661252
  22. C. L. Wang and J. L. Lin, 'Systolic Array Implementation of Multipliers for Finite Field GF($2^m$),' IEEE Trans. Circuits and Syst., vol. 38, no. 7, pp. 796-800, July 1991 https://doi.org/10.1109/31.135751
  23. S. Y. Kung, VLSI Array Processors, Englewood Cliffs, NJ: Prentice Hall, 1988
  24. C.H. Kim and C.P. Hong, 'High-speed division architecture for GF($2^m$),' Electronics Letters, vol. 38, no. 15, pp. 835-836, July 2002 https://doi.org/10.1049/el:20020550
  25. NIST, Recommended elliptic curves for federal government use, May 1999. http://csrc.nist.gov/encryption
  26. Altera, APEXTMII Programable Logic Device Family Data Sheet, Aug. http://www.altera.com/literature/lit-ap2.html