• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.285-290
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• 2023

Compressors are widely used in high-speed electronic systems and are used to reduce the number of operands in multiplier. The proposed compressor is constructed based on the m-GDI(: modified gate diffusion input) to reduce the propagation delay time. This paper is compared the performance of compressors by applying 4-2, 5-2 and 6-2 m-GDI compressors to the multiplier, respectively. As a simulation results, compared to the 8-bit Dadda multiplier using the 4-2 and 6-2 compressor, the multiplier using the 5-2 compressor is reduced propagation delay time 13.99% and 16.26%, respectively. Also, the multiplier using the 5-2 compressor is reduced PDP(: Power Delay Product) 4.99%, 28.95% compared to 4-2 and 6-2 compressor, respectively. However, the multiplier using the 5-2 compression circuit is increased power consumption by 10.46% compared to the multiplier using the 4-2 compression circuit. In conclusion, the 8-bit Dadda multiplier using the 5-2 compressor is superior to the multipliers using the 4-2 and 6-2 compressors. The proposed circuit is implemented using TSMC 65nm CMOS process and its feasibility is verified through SPECTRE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.45-54
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• 2002

This paper proposes serial test data compression, a novel DFT scheme for embedded cores in SOC. To reduce test data amounts, share bit compression and fault undetectable fault pattern compression techniques was used. A Circuits using serial test data compression method are derived from a scan DFT method including a test-per-clock technique. For an experiment of the proposed compression method, full scan versions of ISCASS85 and ISCASS89 were used. ATALANTA has been used for ATPG and fault simulation. The amount of test data has been reduced by maximum 98% comparing with original data.

• Proceedings of the Optical Society of Korea Conference
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• 1991.06a
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• pp.13-17
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• 1991

고반복 레이저의 여기전원에 적합한 3단의 자기펄스 압축 시스템을 제작하고, 시스템의 특성을 고찰하였다. 자기 펄스 압축 시스템의 특성 파라메타는 펄스 변압기의 출력과 펄스파형에 대한 포화 인덕터의 단면적, 코일의 권수가 고려되었다. 실험 결과 3단의 자기 펄스압축 시스템의 최적 조건에서 펄스 압축비와 전류 이득은 각각 22,20 이었다.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2002.11a
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• pp.468-478
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• 2002

고품질의 영상 압축기인 JPEG2000의 기본 압축 코덱인 EBCOT(Embedded Block Coding With Optimized Truncation)를 설계하였다. 영상 압축기에서 Context 추출 구현을 위하여 코드블록(Code block)으로 분할하고, 비트플랜(Bit-Plane)코딩을 했으며, 3가지 패스 그룹으로 분리한 후 ZC, RLC, MR, SC를 하였다. 산술부호화는 덧셈 연산과 쉬프트 연산만을 사용하는 MQ-coder를 사용하였으며, Context들의 누적 확률을 추정하여 테이블을 작성하였고, 압축데이터를 산출하였다. 영상 압축을 위한 엔트로피 코더의 하드웨어 구현은 VHDL를 이용하여 설계를 하고, Synopsys사의 논리 회로 합성 도구를 사용하여 합성을 하였으며, Altera사의 FLEX 10K250 Device를 이용하여 FPGA로 구현하였다.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.11a
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• pp.468-478
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• 2002

고품질의 영상 압축기인 JPEG2000의 기본 압축 코덱인 EBCOT(Embedded Block Coding With Optimized Truncation)를 설계하였다. 영상 압축기에서 Context 추출 구현을 위하여 코드블록(Code block)으로 분할하고, 비트플랜(Bit-Plane)코딩을 했으며, 3가지 패스 그룹으로 분리한 후 ZC, RLC, MR, SC를 하였다. 산술부호화는 덧셈 연산과 쉬프트 연산만을 사용하는 MQ-coder를 사용하였으며, Context들의 누적 확률을 추정하여 테이블을 작성하였고, 압축데이터를 산출하였다. 영상 압축을 위한 엔트로피 코더의 하드웨어 구현은 VHDL를 이용하여 설계를 하고, Synopsys사의 논리 회로 합성 도구를 사용하여 합성을 하였으며, Altera사의 FLEX 10K250 Device를 이용하여 FPGA로 구현하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.89-95
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• 2015

Compresses sensing (CS) technique is beneficial for reducing power consumption of biopotential acquisition circuits in wireless healthcare system. This paper investigates the maximum possible compress ratio for various biopotential signal when the CS technique is applied. By using the CS technique, we perform the compression and reconstruction of typical electrocardiogram(ECG), electromyogram(EMG), electroencephalogram(EEG) signals. By comparing the original signal and reconstructed signal, we determines the validity of the CS-based signal compression. Raw-biopotential signal is compressed by using a psuedo-random matrix, and the compressed signal is reconstructed by using the Block Sparse Bayesian Learning(BSBL) algorithm. EMG signal, which is the most sparse biopotential signal, the maximum compress ratio is found to be 10, and the ECG'sl maximum compress ratio is found to be 5. EEG signal, which is the least sparse bioptential signal, the maximum compress ratio is found to be 4. The results of this work is useful and instrumental for the design of wireless biopotential signal monitoring circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.87-95
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• 2004

This paper proposes a new test data compression/decompression method for SoC(Systems-on-a-Chip). The method is based on analyzing the factors that influence test parameters: compression ratio and hardware overhead. To improve compression ratio, the proposed method is based on Modified Statistical Coding (MSC) and Input Reduction (IR) scheme, as well as a novel mapping and reordering algorithm proposed in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.83-91
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• 2000

This paper presents a new technique to reduce a large interconnect circuit with tens of thousands of elements into the one that is small enough to be analyzed by circuit simulators such as SPICE. This technique takes a fundamentally different approach form the conventional methods based on the interconnect circuit structure analysis and several rules based on the Elmore time constant. The time moments are computed form the circuit consisting of the interconnect circuit and the CMOS gate driver model computed by the AWE technique. Then, the equivalent RC circuit is synthesized from those moments. The characteristics of the driving CMOS gate can be reflected with the high degree of accuracy and the size of the compressed circuit is determined by the number of output nodes regardless of the size of the original interconnect circuits. This technique has been implemented in C language, applied to several interconnect circuits driven by a 0.5${\mu}m$ CMOS gate and the equivalent RC circuits with more than 99% reduction ratio and accuracy with 1 ~ 10% error in therms of propagation delays were obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1045-1054
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• 2002

We present a new low power scan testing and test data compression mothod lot System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low Power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full - scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Proceedings of the Optical Society of Korea Conference
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• 2001.02a
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• pp.238-239
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• 2001

sub-30fs 펄스폭의 상용 Ti：sapphire 레이저시스템에 대한 펄스압축기 및 2차 조화파 발생기를 제작하여 특성을 평가하였다. 그림la에서 82MHz의 주파수로 모드록되는 상용 Ti：sapphire 레이저 (Spectra-Physics Millennia/Tsunami laser)의 출력이 반사경 Ml, M2를 거쳐 펄스압축기에 입사되고 압축되어 나온 펄스가 다시 M6, M7를 거쳐 2차 조화파발생기로 입사되는 2단구조로 설계되었다. 압축기에 입사되기전 평균파워는 파장 800nm에서 520mW로 측정되었으며, 측정된 스펙트럼 반치폭 47nm에 (그림 2a)에 대해 chirp-free sech$^2$t 펄스로 가정할 경우 본 레이저시스템의 변환한계 펄스폭은 14.5fs로 계산된다. (중략)