• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.4
• /
• pp.91-96
• /
• 2014

Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.

• Journal of the Korean institute of surface engineering
• /
• v.47 no.2
• /
• pp.68-74
• /
• 2014

The seed step-coverage enhancement process (SSEP) using Pd/Cu/PVP colloids was investigated for the filling of through silicon via (TSV) without void. TEM analysis showed that the Pd/Cu nano-particles were well dispersed in aqueous solution with the average diameter of 6.18 nm. This Pd/Cu nano-particles were uniformly deposited on the substrate of Si/$SiO_2$/Ti wafer using electrophoresis with the high frequency Alternating Current (AC). After electroless Cu deposition on the substrate treated with Pd/Cu/PVP colloids, the adhesive property between deposited Cu layer and substrate was evaluated. The Cu deposit obtained by SSEP with Pd/Cu/PVP colloids showed superior adhesion property to that on Pd ion catalyst-treated substrate. Finally, by implementing the SSEP using Pd/Cu/PVP colloids, we achieved 700% improvement of step coverage of Cu seed layer compared to PVD process, resulting in void-free filling in high aspect ratio TSV.

• Journal of the Korean Society for Precision Engineering
• /
• v.27 no.10
• /
• pp.40-44
• /
• 2010

Laser drilling is an enabling technology for Through Silicon Via (TSV) interconnect applications. Recent advances in picoseconds laser drilling of blind, micron sized vias in silicon is presented here highlighting some of the attractive features of this approach such as excellent sidewall quality. In this study, we dealt with comparison of heat affection around drilled hole between a picosecond laser and a nanosecond laser process under the UV wavelength. Points which special attention should be paid are that picosecond laser process lowered experimentally recast layer, surface debris and micro-crack around hole in comparison with nanosecond laser process. These finding suggests that laser TSV process has possibility to drill under $10{\mu}m$ via. Finally, the laser drilling platform was constructed successfully.

• KIPS Transactions on Computer and Communication Systems
• /
• v.4 no.2
• /
• pp.41-46
• /
• 2015

The demand on low power and high performance system is soaring due to the extending of mobile and small electronic device market. The 3D die-stacking technology is widely studying for next generation integration technology due to its high density and low access time. We proposed the 3D die-stacked DRAM including a reconfigurable accelerator in a logic layer of DRAM. Also we discuss and suggest a cache-based local memory for a reconfigurable accelerator in a logic layer. The reconfigurable accelerator in logic layer of 3D die-stacked DRAM reduces the overhead of data management and transfer due to the characteristics of its location, so that can increase the performance highly. The proposed system archives 24.8 speedup in maximum.

• Journal of the Microelectronics and Packaging Society
• /
• v.29 no.3
• /
• pp.25-29
• /
• 2022

Recently, the importance of electronic packaging technology has been attracting attention, and heterogeneous integration technology in which chips are stacked out-of-plane direction is being applied to the electronic packaging field. The 2.5D integration circuit is a technology for stacking chips using an interposer including TSV, and is widely used already. Therefore, it is necessary to make the interposer mechanically reliable in the packaging process that undergoes various thermal processes and mechanical loadings. Considering the structural characteristics of the interposer on which several thin films are deposited, thermal stress due to the difference in thermal expansion coefficients of materials can have a great effect on reliability. In this study, the mechanical reliability of the metal pad for wire bonding on the silicon interposer against thermal stress was evaluated. After heating the interposer to the solder reflow temperature, the delamination of the metal pad that occurred during cooling was observed and the mechanism was investigated. In addition, it was confirmed that the high cooling rate and the defect caused by handling promote delamination of the metal pads.

• Korean Chemical Engineering Research
• /
• v.47 no.1
• /
• pp.1-10
• /
• 2009

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional chip cannot be a solution for the enhancement of the semiconductor chip technology due to an increase in RC delay among interconnects. To address this problem, a new technology - "3 dimensional (3D) IC chip stack" - has been emerging. For the integration of the technology, several new key unit processes (e.g., silicon through via, wafer thinning and wafer alignment and bonding) should be developed and much effort is being made to achieve the goal. As a result of such efforts, 4 and 8 chip-stacked DRAM and NAND structures and a system stacking CPU and memory chips vertically were successfully developed. In this article, basic theory, configurations and key unit processes for the 3D IC chip integration, and a current tendency of the technology are explained. Future opportunities and directions are also discussed.