• Journal of the Korean Ceramic Society
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• v.27 no.5
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• pp.645-651
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• 1990

Effects of excess Si on the properities of the oxide of CVD tungsten silicide were investigated by comparing the characteristics of the two kinds of thermal oxide for CVD-WSi2.7 and WSi3.1 films on the polycrystalline Si film each other. It is reveraled from AES analysis that Si in the surface region of the silicide film is consumed to make composition and resistivity of the silicide film very nonuniform for the case of the oxidation of WSi3.1, while the underlayer polycrystalline Si was consumed for the case of the oxidation of WSi2.7.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.454-457
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• 1987

Formation of the titanium silicides was performed by the furnace annealing. Ti-silicide was formed by reacting Ti films with singlecrystalline silicon in vacuum or nitrogen ambient in the temperature range $500{\sim}900^{\circ}C$. The Ti-Si interaction in such films was investigated by using X-ray diffraction, and sheet resistance measurements. It was found that the dorminant crystal phase of silicide formed during annealing at $600{\sim}700^{\circ}C$ was TiSi, and $TiSi_2$ phase is associated with a very low sheet resistance(<$2{\Omega}/{\Box}$).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.6
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• pp.462-465
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• 2009

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method, The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than 10), Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• Journal of the Semiconductor & Display Technology
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• v.4 no.2 s.11
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• pp.7-10
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• 2005

[ $SiO_{2}$ ] or SiON is usually deposited and annealed after formation of silicide in real transistor fabrication processes. Nickel silicide and nickel silicide with Co interlayer were annealed at 650$^{\circ}C$ for 30 min with silica top layer in this study to investigate its thermal stability. SEM, XPS, and FPP(four point probe) were employed for the investigation. Nickel silicide with Co interlayer showed improved thermal stability. Co interlayer seems to play a key role to the stability of nickel silicide.

• ETRI Journal
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• v.8 no.3
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• pp.15-23
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• 1986

ISL(Integrated Schottky Logic)의 고집적화를 위하여 종래의 p-n 접합 격리 방법 대신에 산화막으로 격리시킨 2마이크론의 최소 설계치수를 갖는 소자를 설계, 제작하여 특성을 분석하였다. 접합 형성을 위한 불순물은 이온 주입법을 이용하여 고속소자가 필연적으로 갖추어야 하는 얕은 접합으로 형성을 시켰으며, 출력단의 쇼트키 다이오드는 백금 실리 사이드를 이용하였다. 링 발진기의 특성에서 최소 전달지연 시간은 한 게이트당 5.7ns의 속도 특성과 논리 진폭은 360mV의 현격한 특성을 나타내었다 .

• Journal of the Korean Vacuum Society
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• v.6 no.2
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• pp.143-150
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• 1997

In this study, doffusion barrier properties of 1000 $\AA$ thick molybdenum compound(Mo, Mo-N, $MoSi_2$, Mo-Si-N) films were investigated using sheet resistance measurement, X-ray diffraction(XRD), X-ray photoelectron spectroscopy(XPS), Scanning electron mircoscopy(SEM), and Rutherford back-scattering spectrometry(RBS). Each barrier material was deposited by the dc magnetron sputtering and annealed at 300-$800^{\circ}C$ for 30 min in vacuum. Mo and MoSi2 barrier were faied at low temperatures due to Cu diffusion through grain boundaries and defects in Mo thin film and the reaction of Cu with Si within $MoSi_2$, respectively. A failure temperature could be raised to $650^{\circ}C$-30 min in the Mo barrier system and to $700^{\circ}C$-30 min in the Mo-silicide system by replacing Mo and $MoSi_2$ with Mo-N and Mo-Si-N, respectively. The crystallization temperature in the Mo-silicide film was raised by the addition of $N_2$. It is considered that not only the $N_2$, stuffing effect but also the variation of crystallization temperature affects the reaction of Cu with Si within Mo-silicide. It is found that Mo-Si-N is the more effective barrier than Mo, $MoSi_2$, or Mo-N to copper penetraion preventing Cu reaction with the substrate for $30^{\circ}C$min at a temperature higher than $650^{\circ}C$.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.414.1-414.1
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• 2016

스크린 프린팅법을 이용한 태양전지의 전극은 주로 고가의 은을 사용하기에 태양전지의 저가화에 한계를 가지고 있다. 고효율 결정질 실리콘 태양전지의 원가절감의 문제 해결방안으로 박형 웨이퍼 연구개발이 많은 관심을 받고 있다. 본 연구에서는 은 전극을 대체 할 수 있는 니켈/구리 전극을 사용하였고, 박형 웨이퍼에서도 전극 공정이 가능한 도금법을 사용하여 전극을 형성 하였다. 니켈 전극형성은 광유도 도금법(Light-Induced Plating), 구리 전극형성은 광유도전해도금법(Light-Induced Electro Plating)을 이용하여 실험을 진행 하였다. 니켈 광유도 도금 공정시 공정시간 3 ~ 9분까지 가변하였다. 니켈실리사이드 형성 위해 열처리 공정을 $300{\sim}450^{\circ}C$까지 가변하였고 유지시간 30초 ~ 3분까지 가변하여 실험을 진행하였다. 니켈 도금 수용액의 pH 6 ~ 7.5까지 가변하여 실험하였다. 구리 광유도 전해도금 공정 전류밀도를 $1.6mA/cm^2{\sim}6.4mA/cm^2$까지 가변하여 실험을 진행 후, 전류밀도 $3.2mA/cm^2$로 시간 5 ~ 7분까지 가변하여 실험 하였다. 니켈 도금 공정 시간 5분, 니켈실리사이드 형성 열처리 온도 $350^{\circ}C$, 유지시간 1분에서 DIV(Dark I-V) 분석결과 가장 적은 누설전류를 확인하였다. 니켈 도금액 pH 6.5에서 니켈입자 및 구리입자의 균일성이 좋은 최적의 조건임을 확인하였다. 구리 도금 공정 전류밀도 $3.2mA/cm^2$, 시간 5분에서 TLM(Transmission Line Method) 측정결과 접촉 저항 $0.39{\Omega}$과 접촉 비저항 $12.3{\mu}{\Omega}{\cdot}cm^2$의 저항을 확인하였다. 도금법을 이용하여 전극을 형성함으로써 접촉저항 및 접촉 비저항이 낮고 전극 품질이 향상됨으로서 셀의 전류밀도 $42.49mA/cm^2$를 얻을 수 있었다.

• Korean Journal of Materials Research
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• v.14 no.6
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• pp.389-393
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• 2004

The silicide layer used as a diffusion barrier in microelectronics is typically required to be below 50 nm-thick and, the same time, the silicides also need to have low contact resistance without agglomeration at high processing temperatures. We fabricated Si(100)/15 nm-Ni/15 nm-Co samples with a thermal evaporator, and annealed the samples for 40 seconds at temperatures ranging from $700^{\circ}C$ to $1100^{\circ}C$ using rapid thermal annealing. We investigated microstructural and compositional changes during annealing using transmission electron microscopy and auger electron spectroscopy. Sheet resistance of the annealed sample stack was measured with a four point probe. The sheet resistance measurements for our proposed Co/Ni composite silicide was below 8 $\Omega$/sq. even after annealing $1100^{\circ}C$, while conventional nickel-monosilicide showed abrupt phase transformation at $700^{\circ}C$. Microstructure and auger depth profiling showed that the silicides in our sample consisted of intermixed phases of $CoNiSi_{x}$ and NiSi. It was noticed that NiSi grew rapidly at the silicon interface with increasing annealing temperature without transforming into $NiSi_2$. Our results imply that Co/Ni composite silicide should have excellent high temperature stability even in post-silicidation processes.

• Journal of the Korean Vacuum Society
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• v.7 no.3
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• pp.208-213
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• 1998

Silicidation of the Co/Ti/Si bilayer system in which Ti is used as epitaxy promoter for $CoSi_2$has recently received much attention. The Co/Ti bilayer on the spacer oxide of gate electrode must be thermally stable at high temperatures for a salicide transistor to be fabricated successfully. In the $SiO_2$substrate was rapid-thermal annealed. The Sheet resistances of the Co/Ti bilayer increased substantially after annealing at $600^{\circ}C$, which is due to the agglomeration of the Co layer to reduce the interface energy between the Co layer and the $SiO_2$substrate. In the bilayer system insulating Ti oxide stoichiometric Ti oxide and silicide were not found after annealing.

• Korean Journal of Materials Research
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• v.10 no.12
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• pp.812-818
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• 2000

We studied the effects of Ge preamorphization (PAM) on 0.25$\mu\textrm{m}$ Ti-salicide junctions using comparative study with As PAM. For each PAM schemes, ion implantations are performed at a dose of 2E14 ion/$\textrm{cm}^2$ and at 20keV energy using $^{75}$ /As+and GeF4 ion sources. Ge PAM showed better sheet resistance and within- wafer uniformity than those of As PAM at 0.257m line width of n +/p-well junctions. This attributes to enhanced C54-silicidation reaction and strong (040) preferred orientation of the C54-silicide due to minimized As presence at n+ junctions. At p+ junctions, comparable performance was obtained in Rs reduction at fine lines from both As and Ge PAM schemes. Junction leakage current (JLC) revels are below ~1E-14 A/$\mu\textrm{m}^{2}$ at area patterns for all process conditions, whereas no degradation in JLC is shown under Ge PAM condition even at edge- intensive patterns. Smooth $TiSi_2$ interface is observed by cross- section TEM (X- TEM), which supports minimized silicide agglomeration due to Ge PAM and low level of JLC. Both junction break- down voltage (JBV) and contact resistances are satisfactory at all process conditions.