• Title/Summary/Keyword: 신호변환기

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광회선분배 기술

  • Park, Hyeok;Lee, Chang-Hyeong;Kim, Bong-Gyu;Kim, Gwang-Jun
    • Information and Communications Magazine
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    • v.18 no.11
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    • pp.82-95
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    • 2001
  • OXC는 정적인 점대점 광전송망에서 동적인 그물형 전광통신망으로 진화하기 위하여 망에 도입되어야 할 새로운 광네트워크 장비이다. OXC는 링크 단위의 스위칭을 하는 FXC 파장 단위의 스위칭 기능이 있으나 파장 변환 기능이 없는 WSXC, 그리고 파장 변환 기능이 있는 WIXC로 구분할 수 있으며, 이들간의 hybrid 도 가능하다. OXC 하드웨어의 중심을 이루는 것은 광스위치이다. MEMS 기술, 열광학 효과를 이용한 광도파로 기술, 전반사를 이용하는 bubble 스위치 기술 등을 사용하여 개발이 진행되고 있다. 현재까지는 이 중 3D MEMS 기술이 대용량 스위치를 구성할 가능성이 있는 기술로 받아들여지고 있다. OXC를 구성하는데 있어서 또 다른 핵심적인 기술에는 파장변환 기술이 있다. 광전 파장변환기와 전광 파장변환기 방식이 현재 연구되고 있으며 초기에는 광전변환 방식이 OXC 시스템에 적용될 가능성이 높다. 전광 파장변환기의 시스템 적용을 위해서는 좀 더 많은 연구가 필요할 것으로 보인다. OXC를 사용하는 전광통신망에서 광스위치 기술 이상으로 많은 논란이 되는 것은 망의 운용 문제이다. 현재 가장 많이 언급되는 모델은 오버레이 모델과 피어 모델이다. 오버레이 모델은 클라이언트/서버 개념에 기반한 모델인 반면 피어 모델은 광 네트워크 장비와 기존 장비를 대등한 관계로 정의한 모델이다. 각각의 모델에 대해서는 표준화 단체에 따라 약간씩 다른 입장을 취하고 있지만 상호 간에 수용 또는 타협할 점이 많다고 볼 수 있다. OXC를 포함하는 전광 통신망을 운용할 때에는 동적 연결 설정 및 해제를 위한 새로운 신호 방식이 필요하다. 이를 위하여 ITU-T 및 OIF에서 UNI와 NNI등의 인터페이스와 여기에 사용되는 신호 방식을 논의하고 있다. 그 외에도 전광 통신망 운용에 필요한 라우팅 및 파장할당 방법과 OXC를 이용한 그물형 망에서의 보호 및 복구에 대한 연구도 활발히 진행되고 있다.

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A New Beam Tracking Technique Using Intermediate Frequency Processing (중간주파수 처리를 이용한 빔추적 능동위상 배열안테나)

  • 서철헌;최태규
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.7B
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    • pp.891-894
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    • 2001
  • 본 논문에서는 능동 배열 안테나에서 RF 대신 중간주파수를 이용하여 빔 추적을 하는 방법이 연구되었다. 안테나의 각 배열은 전압제어 발진기, 위상추적기, 혼합기와 결합되어 있으며 혼합기는 안테나 상에서 직접 RF 신호를 직접 중간주파수 신호로 변환시킨다. 전압제어 발진기 입력은 위상추적기에 의하여 조절되며 배열 안테나의 주사범위는 위상추적기와 전압제어발진기에 의하여 결정되었다.

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16kbps Windeband Sideband Speech Codec (16kbps 광대역 음성 압축기 개발)

  • 박호종;송재종
    • The Journal of the Acoustical Society of Korea
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    • v.21 no.1
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    • pp.5-10
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    • 2002
  • This paper proposes new 16 kbps wideband speech codec with bandwidth of 7 kHz. The proposed codec decomposes the input speech signal into low-band and high-band signals using QMF (Quadrature Mirror Filter), then AMR (Adaptive Multi Rate) speech codec processes the low-band signal and new transform-domain codec based on G.722.1 wideband cosec compresses the high-band signal. The proposed codec allocates different number of bits to each band in an adaptive way according to the property of input signal, which provides better performance than the codec with the fixed bit allocation scheme. In addition, the proposed cosec processes high-band signal using wavelet transform for better performance. The performance of proposed codec is measured in a subjective method. and the simulations with various speech data show that the proposed coders has better performance than G.722 48 kbps SB-ADPCM.

The Design of Image Rejection Mixer (이미지 제거 혼합기의 설계)

  • Kang, Eun Kyun;Jeon, Hyung Jun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.5
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    • pp.123-127
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    • 2017
  • This paper fabricated and analyzed the image rejection mixer that uses FET's channel resistance. It can be applied for capacity 64QAM that has 50MHz~90MHz of IF band, 8.17GHz of LO frequency and 8.08~8.12GHz of RF band. When IF input power is -20dBm and LO input power is 10dBm, RF output power is obtained -33.2dBm. In this case, conversion loss is 12.9dB, the suppression of 14.3dB for LO frequency and 10.4dB for image frequency. The result of two tone test shows great IMD characteristics with 51.7dBc.

Hardware Implementation of FPGA-based Real-Time Formatter for 3D Display (3D 디스플레이를 위한 FPGA-기반 실시간 포맷변환기의 하드웨어 구현)

  • Seo Young-Ho;Kim Dong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.5
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    • pp.1031-1038
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    • 2005
  • In this paper, we propose real-time 3D image converting architecture by a unit of pixel for 2D/3D compatible PC and LCD of cellular phone with parallax burier, and implement a system for overall display operation after designing a circuit based on FPGA. After digitizing anolog image signal from PC, we recompose it to 3D image signal according to input image type. Since the architecture which rearranges 2D image to 3D depends on parallax burier, we use interleaving method which mixes pixels by a unit of R, G, and B cell. The propose architecture is designed into a circuit based on FPGA with high-speed memory access technique and use 4 SDRAMs for high performance data storing and processing. The implemented system consists of A/D converting system, FPGA system to formatting 2D signal to 3D, and LCD panel with parallax barrier, for 3D display.

Design of Frequency to Analog-Voltage Converter (주파수-아날로그 전압 변환 회로의 설계)

  • Choi, Jin-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.5
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    • pp.1119-1124
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    • 2011
  • The operation of current conveyor circuit is similar to an operational amplifier and a current conveyor circuit has the characteristics such as good linearity and stability. In this paper, a frequency-to-voltage converter circuit is designed by using a current conveyor circuit. The supply voltage is 5volts and the designed circuit is simulated by HSPICE. The range of the input frequency is from 4kHz to 200kHz. From the simulation results the error of the output voltages is less than from -1.3% to +2.5% compared to the calculated values.

Circuit design of current driving A/D converter (전류 구동형 A/D converter 회로 설계)

  • Lee, Jong-Gyu;Oh, Woo-Jin;Kim, Myung-Sik
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.11
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    • pp.2100-2106
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    • 2007
  • Multi-stage folding A/D converter circuit with $0.25{\mu}m$ N-well CMOS technology is designed. This A/D converter consists of a transconductance circuit, linear folder circuit and 1bit A/D converter circuit. In H-spice simulation results, linear folder circuits having high linearity can be obtained when the current mode is used instead of voltage mode. And in case of 6bit, the delay time is limited about 40ns. From this results, 6bit 25MSPS A/D converter circuit can be realized.

A Fractional-N PLL with Phase Difference-to-Voltage Converter (위상차 전압 변환기를 이용한 Fractional-N 위상고정루프)

  • Lee, Sang-Ki;Choi, Young-Shig
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.12
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    • pp.2716-2724
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    • 2012
  • In this paper, a Phase Difference-to-Voltage Converter (PDVC) has been introduced into a conventional fractional-N PLL to suppress fractional spurs. The PDVC controls charge pump current depending on the phase difference of two input signals to phase frequency detector. The charge pump current decreases as the phase difference of two input signals increase. It results in the reduction of fractional spurs in the proposed fractional-N PLL. The proposed fractional-N PLL with PDVC has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

Design of RF Front-end for High Precision GNSS Receiver (고정밀 위성항법 수신기용 RF 수신단 설계)

  • Chang, Dong-Pil;Yom, In-Bok;Lee, Sang-Uk
    • Journal of Satellite, Information and Communications
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    • v.2 no.2
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    • pp.64-68
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    • 2007
  • This paper describes the development of RF front.end equipment of a wide band high precision satellite navigation receiver to be able to receive the currently available GPS navigation signal and the GALILEO navigation signal to be developed in Europe in the near future. The wide band satellite navigation receiver with high precision performance is composed of L - band antenna, RF/IF converters for multi - band navigation signals, and high performance baseband processor. The L - band satellite navigation antenna is able to be received the signals in the range from 1.1 GHz to 1.6 GHz and from the navigation satellite positioned near the horizon. The navigation signal of GALILEO navigation satellite consists of L1, E5, and E6 band with signal bandwidth more than 20 MHz which is wider than GPS signal. Due to the wide band navigation signal, the IF frequency and signal processing speed should be increased. The RF/IF converter has been designed with the single stage downconversion structure, and the IF frequency of 140 MHz has been derived from considering the maximum signal bandwidth and the sampling frequency of 112 MHz to be used in ADC circuit. The final output of RF/IF converter is a digital IF signal which is generated from signal processing of the AD converter from the IF signal. The developed RF front - end has the C/N0 performance over 40dB - Hz for the - 130dBm input signal power and includes the automatic gain control circuits to provide the dynamic range over 40dB.

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Improvement of the Signal-to-Noise Ratio of Photorefractive Joint Transform Correlator using Characteristics of $BaTiO_3$ ($BaTiO_3$의 특성을 이용한 광굴절 결합 변환 상관기의 신호 대 잡음비 개선)

  • 공명술;서동환;신창목;조규보;김철수;김수중
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.3
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    • pp.19-32
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    • 2003
  • In the conventional photorefractive joint transform correlator(PRJTC), the intensity ration of input signal-to-pump beam should be large enough to saturate two-beam coupling transfer function to obtain a desired correlation result. As a result, the signal-to-noise ratio(SNR) of correlation result is decreased in a noisy input image. In this paper, we propose the improved method for increasing the SNR of the PRJTC by using the characteristics of BaTiO$_3$. We stop the energy transfer saturating by low intensity ratio of input beam and realize a short length of effective interaction in BaTiO$_3$ by making large incident angle of the signal beam. So the gain in high frequency area is decreased and the gain in low frequency area comes up to the saturation gain of the beam coupling transfer function. Therefore the SNR is improved in noisy input image and the PRJTC can be easily realized by low intensity ratio of input beam.