• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1998.12a
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• pp.137-147
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• 1998

RSA 암호 시스템에서 512비트 이상의 큰 정수 소수의 모듈라 멱승 연산이 필요하기 때문에 효율적인 암호화 및 복호화를 위해서는 모듈라 멱승 연산의 고속 처리가 필수적이다. 따라서 본 논문에서는 몫을 추정하여 모듈라 감소를 실행하고 carry-save 덧셈과 중간 곱의 크기를 제한하는 interleaved 모듈라 곱셈 및 감소 기법을 이용하여 모듈라 멱승 연산을 수행하는 고속 모듈라 멱승 연산 프로세서를 논리 자동 합성 기법을 바탕으로 하는 탑다운 선계 방식으로 VHDL을 이용하여 모델링하고 SYNOPSIS 툴을 이용하여 합성 및 검증한 후 XILINX XC4025 FPGA에 구현하여 성능을 평가 및 분석한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.66-73
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• 2002

As floating-point operations become widely used in various applications such as computer graphics and high-definition DSP, the needs for fast division become increased. However, conventional floating-point dividers occupy a large hardware area, and bring bottle-becks to the entire floating-point operations. In this paper, a high-performance and small-area floating-point divider, which is suitable for embedded processors, is designed using he series expansion algorithm. The algorithm is selected to utilize two MAC(Multiply-ACcumulate) units for quadratic convergence to the correct quotient. The two MAC units for SIMD-DSP features are shared and the additional area for the division only is very small. The proposed divider supports all rounding modes defined by IEEE 754 standard, and error estimations are performed for appropriate precision.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1491-1497
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• 2004

The psychoacoustic model in MPEG audio layer-III (MP3) encoder is optimized for the fixed-point processing. The optimization process consists of determining the data word length of arithmetic unit and the algorithm for transcendental functions that are often used in the psychoacoustic model. In order to determine the data word length, we defined a statistical model expressing the relation between the fixed-point operation errors of the psychoacoustic model and the probability of alteration of the allocated bits doe to these errors. Based on the simulations using this model, we chose a 24-bit data path and constructed a 24-bit fixed-point MP3 encoder. Sound quality tests using the constructed fixed-point encoder showed a mean degradation of -0.2 on ITU-R 5-point audio impairment scale.

• The KIPS Transactions:PartA
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• v.13A no.3 s.100
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• pp.185-190
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• 2006

JPEG 2000 is used as an alternative to solve the blocking artifact problem with the existing still image compression JPEG algorithm. However, it has shortcomings such as longer floating point computation time and more complexity in the procedure of enhancing the image compression rate and decompression rate. To compensate for these we implemented with hardware the JPEG 2000 algorithm's filter part which requires a lot of floating point computation. This DWT Filter[1] chip is designed on the basis of Daubechies 9/7 filter[6] and is composed of 3-stage pipeline system to optimize the performance and chip size. Our implemented Filter was 7 times faster than software based Filter in the floating point computation.

• Journal of Educational Research in Mathematics
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• v.17 no.3
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• pp.233-251
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• 2007

The purpose of this study was to propose instructional methods using base-ten blocks in teaching the division of decimal for 5th grade students by analyzing the process of their conceptual comprehension. The students in this study were found to understand the two main meanings of the division of decimal, distribution and area, by modeling them with base-ten blocks. They were able to identify the algorithm through the use of base-ten blocks and to understand the principle of calculations by connecting the manipulative activities to each stage of algorithm. The students were also able to determine using base-ten blocks whether the results of division of decimal might be reasonable. This study suggests that the appropriate use of base-ten blocks promotes the conceptual understanding of the division of decimal.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.1035-1037
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• 2007

Ad-hoc 네트워크는 자율적으로 네트워크를 구성함으로써 유연하고 확장 가능한 특성을 가진다. 하지만 익명으로 구성되는 네트워크의 특성은 사용자의 안전을 보장하지 못함으로 Ad-hoc 네트워크 활성화에 걸림돌이 되고 있다. 여기서는 소수의 악의적인 공격자가 있는 경우에 높은 확률로 연산 결과를 신뢰할 수 있는 안전한 연산 기법들을 활용하여 Ad-hoc 네트워크에서 이루어지는 연산을 보다 안전하게 수행할 수 있는 방안을 제안한다.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.775-778
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• 2000

2채널의 MPEG-2 Layer-Ⅲ 오디오 복호화 알고리듬이 16비트의 고정소수점 연산기로도 고음질의 오디오출력을 얻을 수 있도록 최적화를 수행하였다. 고음질을 얻기 위하여 고정소수점 연산기에서 발생하는 양자화 오차를 최소화 하였으며 각 복호화 과정 별로 최소의 오차를 발생시키는 알고리듬을 제안하고 사용하였다. 고정소수점 모의실험은 C-언어를 사용하여 수행되었으며, ISO-IEC 13818-4 Compliance Test를 수행하여 최적화된 복호화기가 ISO／IEC 13818-4 audio decoder의 기준을 만족함을 보였다.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.53-56
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• 2004

본 논문은 HMM 기반 임베디드 음성인식 시스템 구현에 관한 몇 가지 주제들을 설명한다. 임베디드 환경은 한정된 자원을 가지고 있고 그러한 가운데 타당한 인식률과 향상된 인식 속도를 얻기 위해서 몇가지 방법들을 이 논문에서 설명한다. 구현 환경은 DSP6711 기반에서 이루어졌다. 가우시안 mixture 계산 루틴을 부동소수점 연산에서 고정소수점 연산 및 software pipelining을 적용하였다. 고정소수점 변환 전과 후 비슷한 인식률을 얻었고 고정소수점 변환과 software pipelining 적용 후 연산 속도의 향상을 얻었다.

• Journal of IKEEE
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• v.17 no.3
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• pp.346-351
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• 2013

Low-cost and low-power are important requirements in mobile systems. Thus, when a floating-point arithmetic unit is needed, 24-bit floating-point format can be more useful than 32-bit floating-point format. However, a 24-bit floating-point arithmetic unit can be risky because it usually has lower accuracy than a 32-bit floating-point arithmetic unit. Consecutive floating-point operations are performed in 3D graphic processors. In this case, the verification of the floating-point operation accuracy is important. Among 3D graphic arithmetic operations, the floating-point division is one of the most difficult operations to satisfy the accuracy of $10^{-5}$ which is the required accuracy in OpenGL ES 3.0. No 24-bit floating-point divider, whose accuracy is algebraically verified, has been reported. In this paper, a 24-bit floating-point divider is analyzed and it is algebraically verified that its accuracy satisfies the OpenGL requirement.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.12
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• pp.2921-2926
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• 2013

In this paper, a decimal floating-point arithmetic unit(DFP) was proposed and redesigned to support high speed arithmetic operation employed parallel processing technique. The basic architecture of the proposed DFP was based on the L.K.Wang's DFP and improved it enabling high speed operation by parallel processing for two operands with same size of exponent. The proposed DFP was synthesized as a target device of xc2vp30-7ff896 using Xilinx ISE and verified by simulation using Flowrian tool of System Centroid co. Compared to L.K.Wang's DFP and reference [6]'s method, the proposed DFP improved data processing speed about 8.4% and 3% respectively in case of same input data.