IEEE-754 Floating-Point Divider for Embedded Processors

내장형 프로세서를 위한 IEEE-754 고성능 부동소수점 나눗셈기의 설계

  • Jeong, Jae-Won (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Hong, In-Pyo (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Jeong, Woo-Kyong (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Lee, Yong-Surk (Department of Electrical and Electronic Engineering, Yonsei University)
  • 정재원 (延世大學校 電氣電子工學科) ;
  • 홍인표 (延世大學校 電氣電子工學科) ;
  • 정우경 (延世大學校 電氣電子工學科) ;
  • 이용석 (延世大學校 電氣電子工學科)
  • Published : 2002.07.01

Abstract

As floating-point operations become widely used in various applications such as computer graphics and high-definition DSP, the needs for fast division become increased. However, conventional floating-point dividers occupy a large hardware area, and bring bottle-becks to the entire floating-point operations. In this paper, a high-performance and small-area floating-point divider, which is suitable for embedded processors, is designed using he series expansion algorithm. The algorithm is selected to utilize two MAC(Multiply-ACcumulate) units for quadratic convergence to the correct quotient. The two MAC units for SIMD-DSP features are shared and the additional area for the division only is very small. The proposed divider supports all rounding modes defined by IEEE 754 standard, and error estimations are performed for appropriate precision.

최근 컴퓨터 그래픽이나 고급 DSP 등 부동소수점 연산의 활용 분야가 늘어나면서 나눗셈 연산의 필요성이 증대되었으나, 기존의 나눗셈 연산기는 큰 하드웨어 면적을 차지할 뿐만 아니라 전체 부동소수점 연산의 병목현상을 초래하는 중요한 요인이 되고 있다. 본 논문에서는 급수 전개 알고리즘을 이용한 내장형 프로세서에 적합하도록 소면적의 부동소수점 나눗셈기를 설계하였다. 나눗셈기는 SIMD-DSP 유닛의 두 개의 곱셈누적기를 공유하여 연산함으로써, 부동소수점 단정도 형식의 나눗셈 연산을 고속으로 수행함과 동시에 나눗셈 연산을 위한 추가 면적을 최소화하였다. 본 논문에서는 급수 전개 알고리즘 나눗셈 연산기를 설계함에 있어 고려되어야할 오차의 분석을 통해 정확한 라운딩을 위한 몫을 얻어낼 수 있는 구조를 선택하였으며, IEEE-754 표준에서 정의하고 있는 모든 라운딩 모드를 지원하도록 하였다.

Keywords

References

  1. Stuart F. Oberman and Michael J. Flynn, 'Division Algorithms and Implementations,'IEEE Transactions on Computers, Vol. 46, No. 8, August 1997 https://doi.org/10.1109/12.609274
  2. Peter Soderquist and Miriam Leeser, 'Division and Square Root Choosing the RightImplementation,' IEEE Micro, July 1997, pp. 56-66 https://doi.org/10.1109/40.612224
  3. Peter Soderquist and Miriam Leeser, 'An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations,' Proc. 12th IEEE Symp. Computer Arithmetic, IEEE, 1995, pp. 132-139 https://doi.org/10.1109/ARITH.1995.465366
  4. Stuart F. Oberman and Michael J. Flynn, 'Design Issues in Division and Other Floating-Point Operations,' IEEE Transactions on Computers, Vol. 46, No. 2, Feb. 1997, pp. 154-161 https://doi.org/10.1109/12.565590
  5. D. DasSarma and D. Matula, 'Measuring the Accuracy of ROM Reciprocal Tables,' IEEE Transactions on Computers, Vol. 43, No. 8, pp. 932-940, August 1994 https://doi.org/10.1109/12.295855
  6. Robert E. Goldschmidt, 'Applications of Division by Convergence,' MS thesis, Dept. of Electrical Eng., Massachusetts Inst. of Technology, Cambridge, Mass., June 1964
  7. Stuart F. Oberman, 'Design Issues in High Performance Floating Point Arithmetic Units,' Ph.D. thesis, Stanford University, Nov. 1996
  8. Stuart F. Oberman, 'Floating Point Division and Square Root Algorithms and Implementation in the AMD-K7TM Microprocessor,' Proc. 14th IEEE Symp. on Computer Arithmetic, pp. 106-115, 1999 https://doi.org/10.1109/ARITH.1999.762835