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IEEE-754 Floating-Point Divider for Embedded Processors  

Jeong, Jae-Won (Department of Electrical and Electronic Engineering, Yonsei University)
Hong, In-Pyo (Department of Electrical and Electronic Engineering, Yonsei University)
Jeong, Woo-Kyong (Department of Electrical and Electronic Engineering, Yonsei University)
Lee, Yong-Surk (Department of Electrical and Electronic Engineering, Yonsei University)
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Abstract
As floating-point operations become widely used in various applications such as computer graphics and high-definition DSP, the needs for fast division become increased. However, conventional floating-point dividers occupy a large hardware area, and bring bottle-becks to the entire floating-point operations. In this paper, a high-performance and small-area floating-point divider, which is suitable for embedded processors, is designed using he series expansion algorithm. The algorithm is selected to utilize two MAC(Multiply-ACcumulate) units for quadratic convergence to the correct quotient. The two MAC units for SIMD-DSP features are shared and the additional area for the division only is very small. The proposed divider supports all rounding modes defined by IEEE 754 standard, and error estimations are performed for appropriate precision.
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