• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.540-543
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• 2013

This paper describes an implementation of a unified ALU on multi-core GPGPU based on SIMT architecture. Our unified ALU can operate conditional branch instructions, data movement instructions, integer arithmetic instructions and floating-point arithmetic instructions. Since multi-core GPGPU contains a lot of ALU for parallel processing of various types, the main point of this paper is to design the minimum size ALU by unifying similar processing of each operations on circit level. All instrunctions were tested by making a test program. And we compare this results with results of CPU operations to verify our ALU. Our unified ALU's gate size is approximately 20,000 and the maximum operation frequency is 430MHz.

• Korean Journal of Cognitive Science
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• v.18 no.2
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• pp.159-178
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• 2007

Lee & Kang (2002) showed that simultaneous phonological rehearsal significantly delayed the performance of multiplication but not subtraction, whereas holding an image in the memory delayed subtraction but not multiplication. This result indicated that arithmetic function is related to working memory in a subsystem-specific manner. The aim of the current study was to examine the neural correlates of previous finding using fMRI. For this goal, dual task conditions that required suppression or no suppression were manipulated. In general, several areas were more activated in the interference conditions than in the less interference conditions, although both conditions were dual condition. More important finding is that the specific areas activated in the phonological suppression rendition were right inferior frontal gyrus, left angular, and inferior parietal lobule, while the areas activated in the other condition were mainly in the right superior temporal gyrus and anterior cingulate gyrus. Furthermore, the areas activated in the phonological or visual less suppression condition were right medial frontal gyrus, left middle frontal gyrus, and bilateral medial frontal gyri, anterior cingulate cortices, and parahippocampal gyri, respectively. These results revealed that sharing the processing code invokes interference, and its neural basis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.75-82
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• 2000

In this paper, a new low power 16-bit ALU has been designed, fabricated and tested at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For the reduction of switched capacitance, the ELM adder of the proposed ALU is inactive while the logical operation is performed and P(propagation) block has a dual bus architecture. A new efficient P and G(generation) blocks are also proposed for the above ALU architecture. ELM adder, double-edge triggered register and the combination of logic style are used for low power consumption as well. As a result of simulations, the proposed architecture shows better power efficient than conventional architecture$^{[1,2]}$ as the number of logic operation to be performed is increased over that of arithmetic to logic operation to be performed is 7 to 3, compared to conventional architecture. The proposed ALU was fabricated with 0.6${\mu}m$ single-poly triple-metal CMOS process. As a result of chip test, the maximum operating frequency is 53MHz and power consumption is 33mW at 50MHz, 3.3V.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1991.10a
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• pp.86-91
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• 1991

A capability of performing the optical logic and arithmetic operations is followed by an effective encoding technique. In this paper, we proposed the color light encoding technique. By using this encoding technique, the space bandwidth product(SBP) is minimized in the output plane. In addition, we proposed the pre-operation pro-carry processing method that performs faster than the same time operation and carry processing method in optical computing. We proposed that the color liquid crystal device(CLCD) is used as the encoded color light input source.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.649-654
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• 2011

In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• The Mathematical Education
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• v.50 no.1
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• pp.41-59
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• 2011

Given the importance of algebra in the early grades, this paper analyzed the contents of whole numbers and their operations from the perspectives of generalized arithmetic. In particular, the focus of analysis was given to the properties of 0 and 1, those of operations such as commutativity, associativity, and distributivity, and the relations between operations. As such, this paper analyzed in detail how such properties and relations were introduced and expanded across different grades. It is expected that many issues in this paper will serve basic information to develop instructional materials in a way to fostering students' algebraic thinking in the elementary grades.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.101-108
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• 2017

As the quantum gate matrix is a $r^{n+1}{\times}r^{n+1}$ dimension when the radix is r, the number of control state vectors is n, and the number of target state vectors is one, the matrix dimension with increasing n is exponentially increasing. If the number of control state vectors is $2^n$, then the number of $2^n-1$ unit matrix operations preserves the output from the input, and only one can be performed the unitary operation to the target state vector. Therefore, this paper proposes a new method of function embedding that can replace $2^n-1$ times of unit matrix operations with deterministic contribution to matrix dimension by arithmetic power switch of the unitary gate. The proposed function embedding method uses a binary literal switch with a multivalued threshold, so that a general purpose hybrid MCU gate can be realized in a $r{\times}r$ unitary matrix.

• Communications of Mathematical Education
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• v.28 no.3
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• pp.375-394
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• 2014

The purpose of this study is to examine the transition of mathematical representation in Joseon mathematics, which is focused on numbers and operations, letters and expressions. In Joseon mathematics, there had been two numeral systems, one by chinese character and the other by counting rods. These systems were changed into the decimal notation which used Indian-Arabic numerals in the late 19th century passing the stage of positional notation by Chinese character. The transition of the representation of operation and expressions was analogous to that of representation of numbers. In particular, Joseon mathematics represented the polynomials and equations by denoting the coefficients with counting rods. But the representation of European algebra was introduced in late Joseon Dynasty passing the transitional representation which used Chinese character. In conclusion, Joseon mathematics had the indigenous representation of numbers and mathematical symbols on our own. The transitional representation was found before the acceptance of European mathematical representations.

• Journal of Educational Research in Mathematics
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• v.21 no.3
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• pp.239-259
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• 2011

This study investigated the elementary school students' ability on the algebraic reasoning as generalized arithmetic. It analyzed the written responses from 648 second graders, 688 fourth graders, and 751 sixth graders using tests probing their understanding of the properties of whole number operations. The result of this study showed that many students did not recognize the properties of operations in the problem situations, and had difficulties in applying such properties to solve the problems. Even lower graders were quite successful in using the commutative law both in addition and subtraction. However they had difficulties in using the associative and the distributive law. These difficulties remained even for upper graders. As for the associative and the distributive law, students had more difficulties in solving the problems dealing with specific numbers than those of arbitrary numbers. Given these results, this paper includes issues and implications on how to foster early algebraic reasoning ability in the elementary school.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.112-120
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• 2013

In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.