• Investigative Magnetic Resonance Imaging
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• v.7 no.1
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• pp.12-21
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• 2003

Purpose : In order to overcome limitations in the existing conventional spectrometer, a new spectrometer with advanced functionalities is designed and implemented. Materials and Methods : We designed a spectrometer using the TMS320C6701 DSP capable of 1 giga floating point operations per second (GFLOPS). The spectrometer can generate continuously varying complicate gradient waveforms by real-time calculation, and select image plane interactively. The designed spectrometer is composed of two parts: one is DSP-based digital control part, and the other is analog part generating gradient and RF waveforms, and performing demodulation of the received RF signal. Each recover board can measure 4 channel FID signals simultaneously for parallel imaging, and provides fast reconstruction using the high speed DSP. Results : The developed spectrometer was installed on a 1.5 Tesla whole body MRI system, and performance was tested by various methods. The accurate phase control required in digital modulation and demodulation was tested, and multi-channel acquisition was examined with phase-array coil imaging. Superior image quality is obtained by the developed spectrometer compared to existing commercial spectrometer especially in the fast spin echo images. Conclusion : Interactive control of the selection planes and real-time generation of gradient waveforms are important functions required for advanced imaging such as spiral scan cardiac imaging. Multi-channel acquisition is also highly demanding for parallel imaging. In this paper a spectrometer having such functionalities is designed and developed using the TMS320C6701 DSP having 1 GFLOPS computational power. Accurate phase control was achieved by the digital modulation and demodulation techniques. Superior image qualities are obtained by the developed spectrometer for various imaging techniques including FSE, GE, and angiography compared to those obtained by the existing commercial spectrometer.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.2
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• pp.128-136
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• 2002

In this paper, we developed an acoustic echo canceller in real-time using TeakLite DSP Core, which will be placed in the vocoder chip of a mobile handset. Considering the limited computational capacity given to the acoustic echo canceller in a vocoder chip, we employed a FIR-type adaptive filter using a conventional NLMS algorithm. To begin with, we designed and implemented an acoustic echo canceller with floating-point format C-source code, and then converted it into fixed-point format through integer simulation. Then we programmed and optimized it in the assembler level to make it run ill real-time. After optimization procedure, the implemented echo canceller has approximately 624 words of program memory and 811 words of data memory. With 8 KHz sampling rate and 256 filter taps in the echo canceller that corresponds to 32 msec of echo delay, it requires 14.12 MIPS of computational capacity. For coverage of 16 msec echo delay, i.e., 128 filter taps, 9 MIPS is requited.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.2
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• pp.71-79
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• 2008

High voltage distribution lines in the electric railway system placed according track with communication lines and signal equipments. Case of the over head lines is occurrence the many fault because lightning, rainstorm, damage from the sea wind and so on. According this fault caused protection device to wrong operation. One line ground fault that occurs most frequently in railway high voltage distribution lines and sort of faults is line short, three line ground breaking of a wire, and so on. For this reason we need precise maintenance for prevent of the faults. The most important is early detection and fast restoration in time of fault for a safety transit. In order to develop an advanced fault location device for 22.9[kV] distribution power network in electric railway system this paper deals with new fault locating algorithm using flow technique which enable to determine the location of the fault accurately. To demonstrate its superiorities, the case studies with the algorithm and the fault analysis using PSCAD/EMTDC (Power System Computer Aided Design/Electro Magnetic Transients DC Analysis Program) were carried out with the models of direct-grounded 22.9[kV] distribution network which is supposed to be the grounding method for electric railway system in Korea.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.53-58
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• 2006

A Vertex Shader is designed to show more 3D graphics expressions, and to increase flexibility of the fixed function T&L (Transform and Lighting) engine. Design of this Shader is based on Vertex Shader 1.1 of DirectX 8.1 and OpenGL ARB. The Vertex Shader consists of four floating point ALUs for vectors operation. The previous 32bits floating point data type is replaced to 24bits floating point data type in order to design the Vertex Shader that consume low-power and occupy small area. A Xilinx Virtex2 300M gate module is used to verify behaviour of the core. The result of Synopsys synthesis shows that the proposed Vertex Shader performs 115MHz speed at the TSMC 0.13um process and it can operate as the rate of 12.5M Polygons/sec. It shows the complexity of 110,000 gates in the same process.

• Journal of Korea Multimedia Society
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• v.14 no.2
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• pp.210-218
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• 2011

Generally, GIS digital map has been represented and transmitted by ASCII and Binary data forms. Among these forms, Binary form has been widely used in many GIS application fields for the transmission of mass map data. In this paper, we present a hierarchical compression technique of polyline and polygon components for effective storage and transmission of vector map with various degree of decision. These components are core geometric components that represent main layers in vector map. The proposed technique performs firstly the energy compaction of all polyline and polygon components in spatial domain for the lossless compression of detailed vector map and compress independently integer parts and fraction parts of 64bit floating points. From experimental results, we confirmed that the proposed technique has superior compressive performance to the conventional data compression of 7z, zip, rar and gz.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.1864-1865
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• 2006

무인지능형로봇 시스템에 있어서 자세의 정확도를 향상시키기 위한 많은 연구가 이루어져 왔다. 시스템의 자세 제어는 사용되는 모터의 위치 제어로 대응된다. 이와 같은 시스템은 운용 시에 충격 진동이 발생하게 된다. 이러한 충격 진동 외란을 잘 제거해야 요구되는 위치 정도로 제어를 수행할 수 있다. 로봇 제어 분야에서 불확실한 로봇에 대한 자세 제어 분야는 가장 기본적이면서 중요한 분야중의 하나이다. 이러한 문제를 다루기 위하여 계산 토크 방식에 기초한 선형 제어 기법이나 적응 제어 기법, 강인 제어 기법 등을 이용한 연구 결과들이 발표되고 있다. 그러나 그러한 기법은 일반적으로 로봇의 정확한 동력학식을 알아야 하며, 구현하기 복잡하다. 따라서 본 논문에서는 적응 규칙에 의하여 모델의 불확실성, 시스템의 변화, 외란으로 인해 발생하는 공칭 플랜트와의 오차를 보상하도록 제어 입력을 생성하는 내부 루프 부분과 공칭 플랜트 모델의 명령을 추종하도록 하는 제어 입력을 생성하는 외부 루프 부분으로 구성되는 방법인 외란관측기(Disturbance OBserver : DOB) 제어 알고리즘을 제안한다. 또한 프로세서의 신뢰성과 수치 연산 및 알고리즘의 빠른 처리를 위해 현재 사용 빈도가 높은 TI사의 DSP시리즈 중에서 부동 소수점 연산 기능을 가지면서 모터 제어에 적합한 TMS320C2000계열의 TMS320F2812을 사용하여, 운용 시 발생되는 진동 둥에 대한 외란 제거를 목적으로 한다. 본 논문은 규명된 시스템 모델식을 바탕으로 DOB 제어 시뮬레이션을 수행하고 PMSM 모터모델 시뮬링크 블록을 구성하여 검증된 외란 관측기 제어 알고리즘을 검증한다. 시뮬레이션으로 검증된 DOB 모터 자세 제어 알고리즘을 DSP에 적용하기 위해 코드변환하고 모터 실험 시스템에 실제 적용함으로써 타당성을 검증하여 상용 제어기로 실제 현장에 적용 가능함을 입증한다.

• Journal of the Korean Geographical Society
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• v.33 no.1
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• pp.75-91
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• 1998

The purpose of this paper is to investigate office location dynamic in Seoul and to analyze comparatively the office activities of emerging office centers. Since mid 1980s, the expansion of office employment and spatial differentiation of the office-type jobs have changed the employment and spatial structure of Seoul. The major employment centers are CBD, Kangnam district and Youido. Among these, CBD and Kangnam have developed as the two leading centers of Seoul. Youido, the typical office-oriented center, shares CBD functions especially specializing security business. Selective decentralization of offices made qualitative differences among the centers. In spite of vigorous office decentralization, CBD has kept the principal offices of finance and insurance, travel agencies, advertising agencies, management consulting firms, major public institutions and headquarters of upper 100 companies in Korea. But the offices of producer services such as law, architects, engineering and computer consulting and real estates and headquarters of upper 5000 companies in Korea have been decentralized dominantly to Kangnam.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.140-142
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• 2011

In this paper, special purpose arithmetic unit for mobile graphics accelerator is designed. The designed processor supports six operations, such as $1/{\chi}$, $\frac{1}{{\sqrt{x}}$, $log_2x$, $2^x$, $sin(x)$, $cos(x)$. The processor adopts 2nd-order polynomial minimax approximation scheme based on IEEE floating point data format to satisfy accuracy conditions and has 5-stage pipeline structure to meet high operational rates. The SFAU processor consists of 23,000 gates and its estimated operating frequency is about 400 Mhz at operating condition of 65nm CMOS technology. Because the processor can execute all operations with 5-stage pipeline scheme, it has about 400 MOPS(million operations per second) execution rate. Thus, it can be applicable to the 3D mobile graphics processors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.4
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• pp.727-736
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• 2009

In this paper, the $arccos(cos^{-1})$ arithmetic unit for mobile graphics accelerator is designed. The mobile vector graphics applications need tight area, execution time, power dissipation, and accuracy constraints compared to desktop PC applications. The designed processor adopts 2nd-order polynomial approximation scheme based on IEEE floating point data format to satisfy speed and accuracy conditions and reduces area via hardware sharing structure. The arccosine processor consists of 15,280 gates and its estimated operating frequency is about 125Mhz at operating condition of $0.35{\mu}m$ CMOS technology. Because the processor can execute arccosine function within 7 clock cycles, it has about 17 MOPS(million arccos operations per second) execution rate and can be applicable to mobile OpenVG processor. And because of its flexible architecture, it can be applicable to the various transcendental functions such as exponential, trigonometric and logarithmic functions via replacement of ROM and minor hardware modification.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12A
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• pp.1387-1395
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• 2004

Turbo decoder inherently requires large memory and intensive hardware complexity due to iterative decoding, despite of excellent decoding efficiency. To decrease the memory space and reduce hardware complexity, various design issues have to be discussed. In this paper, various design issues on Turbo decoder are investigated and the tradeoffs between the hardware complexity and the performance are analyzed. Through the various simulations on the fixed-length analysis, we decided 5-bits for the received data, 6-bits for a priori information, and 7-bits for the quantization state metric, so the performance gets close to that of infinite precision. The MAX operation which is the main function of Log-MAP decoding algorithm is analyzed and the error correction term for MAX* operation can be efficiently implemented with very small hardware overhead. The size of the sliding window was decided as 32 to reduce the state metric memory space and to achieve an acceptable BER.