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Performance Analysis on Various Design Issues of Turbo Decoder  

Park Taegeun (가톨릭대학교 정보통신전자공학부)
Kim Kiwhan (가톨릭대학교 컴퓨터공학과)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.29, no.12A, 2004 , pp. 1387-1395 More about this Journal
Abstract
Turbo decoder inherently requires large memory and intensive hardware complexity due to iterative decoding, despite of excellent decoding efficiency. To decrease the memory space and reduce hardware complexity, various design issues have to be discussed. In this paper, various design issues on Turbo decoder are investigated and the tradeoffs between the hardware complexity and the performance are analyzed. Through the various simulations on the fixed-length analysis, we decided 5-bits for the received data, 6-bits for a priori information, and 7-bits for the quantization state metric, so the performance gets close to that of infinite precision. The MAX operation which is the main function of Log-MAP decoding algorithm is analyzed and the error correction term for MAX* operation can be efficiently implemented with very small hardware overhead. The size of the sliding window was decided as 32 to reduce the state metric memory space and to achieve an acceptable BER.
Keywords
Turbo Codes; Turbo Decoder; 3epp; Log-MAP;
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