• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.11
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• pp.1-7
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• 2018

In a microcolumn, a miniaturized electrostatic deflector is often adopted to scan an electron beam. Usually, a double octupole deflector is used because it can avoid excessive spherical aberrations by controlling the electron beam path close to the optical axis of the objective lens and has a wide scan field. Studies on microcolumns have been performed to improve the low throughput of an electron column through multiple column applications. On the other hand, as the number of microcolumns increases, the number of wires connected to the components of the microcolumn increases. This will result in practical problems during the process of connecting the wires to electronic controllers outside of the vacuum chamber. To reduce this problem, modified quadrupole and octupole deflectors were examined through simulation analysis by selecting an ultraminiaturized microcolumn with the Einzel lens eliminated. The modified deflectors were designed changing the size of each electrode of the conventional Si octupole deflector. The variations of the scan field and electric field strength were studied by changing the size of active electrodes to which the deflection voltage was to be applied. The scan field increased linearly with increasing deflection voltage. The scan field of the quadrupole deflector and the electric field strength at the center were calculated to be approximately 1.3 ~ 2.0 times larger than those of the octupole deflector depending on the electrode size.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.1
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• pp.49-54
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• 2022

The copper plating process used to fabricate the submicron damascene pattern of Cu wiring for Si wafer was applied to the plating of a PCB pattern of several tens of microns in size using the same organic additives and current density conditions. In this case, the non-uniformity of the plating thickness inside the pattern was observed. In order to quantitatively analyze the cause, a numerical calculation considering the solution flow and electric field was carried out. The calculation confirmed that the depletion of Cu²⁺ ions in the solution occurred relatively earlier at the bottom corner than the upper part of the pattern due to the plating of the sidewall and the bottom at the corner of the pattern bottom. The diffusion coefficient of Cu²⁺ ions is 2.65 10^-10 m²/s, which means that Cu²⁺ ions move at 16.3 ㎛ per second on average. In the cases of small damascene patterns, the velocity of Cu²⁺ ions is high enough to supply sufficient ions to the inside of the patterns, while sufficient time is required to replenish the exhausted copper ions in the case of a PCB pattern having a size of several tens of microns. Therefore, it is found that the thickness uniformity can be improved by reducing the current density to supply sufficient copper ions to the target area.

• Journal of the Microelectronics and Packaging Society
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• v.31 no.2
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• pp.36-44
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• 2024

Copper electrodeposition technology is essential for producing copper films and interconnects in the microelectronics industries including semiconductor packaging, semiconductors and secondary battery, and there are extensive efforts to control the microstructure of these films and interconnects. In this study, we investigated the influence of crystallographic orientation on the local plastic deformation of copper films for secondary batteries deformed by uniaxial tensile load. Crystallographic orientation maps of two electrodeposited copper films with different textures were measured using an electron backscatter diffraction (EBSD) system and then used as initial conditions for crystal plasticity finite element analysis to predict the local plastic deformation behavior within the films during uniaxial tension deformation. Through these processes, the changes of the local plastic deformation behavior and texture of the films were traced according to the tensile strain, and the crystal orientations leading to the inhomogeneous plastic deformation were identified.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.49-53
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• 2018

Since various methods to form well-aligned nano-/micro- patterns are underlying technologies to fabricate next generation wearable electronic devices, many efforts have been made to realize finer patterns in recent years. Among lots of patterning methods, the present invention includes a nano-transfer printing (n-TP) process which is advantageous in that a processing cost is low and high-resolution patterns can be formed within a short processing time. We successfully achieved pattern formation of highly ordered Pt lines with line-width of 250 nm, 500 nm, and $1{\mu}m$ on transparent and flexible substrates. In addition, we analyzed the durability of the patterns, showing excellent stability of line-shape even after a physical and repeated bending test of 500 times using a bending machine. As a result, it is expected that a n-TP process is very useful for forming various metal patterns, and it is also expected to be applied to wiring and interconnection technology of next generation flexible electronic devices.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.61-66
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• 2018

This research scrutinizes the self-annealing characteristics of copper used to metal interconnection for application of DRAM fabrication process. As the time goes after the copper deposited, the grain of copper is growing. It is called self-annealing. We use the electroplating method for copper deposition and estimate two kinds of electroplating chemicals having different organic additives. As the time of self-annealing is elapsed, sheet resistance decreases with logarithmic dependence of time and is finally saturated. The improvement of sheet resistance is approximately 20%. The saturation time of experimental sample is shorter than that of reference sample. We can find that self-annealing is highly efficient in grain growth of copper through the measurement of TEM analysis. The structure of copper grain is similar to the bamboo type useful for current flow. The results of thermal excursion characteristics show that the reliability of self-annealed sample is better than that of sample annealed at higher temperature. The self-annealed sample is not contained in hillock. The self-annealed samples grow until $2{\mu}m$ and develop in [100] direction more favorable for reliability.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.3 s.40
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• pp.1-8
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• 2006

Higher density integration and adoption of new materials in advanced electronic package systems result in severe electrochemical reliability issues in microelectronic packaging due to higher electric field under high temperature and humidity conditions. Under these harsh conditions, metal interconnects respond to applied voltages by electrochemical ionization and conductive filament formation, which leads to short-circuit failure of the electronic package. In this work, in-situ water drop test and evaluation of corrosion characteristics for SnPb solder alloys in D.I. water and NaCl solutions were carried out to understand the fundamental electrochemical migration characteristics and to correlate each other. It was revealed that electrochemical migration behavior of SnPb solder alloys was closely related to the corrosion characteristics, and Pb was primarily ionized in both D.I. water and $Cl^{-}$ solutions. The quality of passive film formed at film surface seems to be critical not only for corrosion resistance but also for ECM resistance of solder alloys.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.11-17
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• 2010

The electromigration phenomenon in lead-free flip-chip solder joint has been one of the serious problems. To understand the mechanism of this phenomenon, the crystallographic orientation of Sn grain in the Sn-Ag-Cu solder bump has been analyzed. Different time to failure and different microstructural changes were observed in the all test vehicle and bumps, respectively. Fast failure and serious dissolution of Cu electrode was observed when the c-axis of Sn grain parallel to electron flow. On the contrary of this, slight microstructural changes were observed when the c-axis of Sn perpendicular to electron flow. In addition, underfill could enhance the electromigration reliability to prevent the deformation of solder bump during EM test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.137-145
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• 2008

In this paper, novel CMOS charge pump having NMOS and PMOS transfer switches and a bulk-pumping circuit has been proposed. The NMOS and PMOS transfer switches allow the charge pump to improve the current-driving capability at the output. The bulk-pumping circuit effectively solves the bulk forward problem of the charge pump. To verify the effectiveness, the proposed charge pump was designed using a 80-nm CMOS process. The comparison results indicate that the proposed charge pump enhances the current-driving capability by more than 47% with pumping speed improved by 9%, as compared to conventional charge pumps having either NMOS or PMOS transfer switch. They also indicate that the charge pump reduces the worst-case forward bias of p-type bulk by more than 24%, effectively solving the forward current problem.

• Journal of the Korean Vacuum Society
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• v.16 no.6
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• pp.439-445
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• 2007

SiGe integrated circuits are being used in the field of high-speed wire/wireless communications and microwave systems due to the RF/high-speed analog characteristics and the easiness in the fabrication. Reducing the resistance variation in SiGe thin film resistors results in enhancing the reliability of integrated circuits. In this paper, we investigate the causes that generate the resistance nonuniformity after the silicon-based thin film resistor was fabricated, and consider the counter plan against that. Because the Ti-B precipitate, which formed during the silicide process of the SiGe thin film resistor, gives rise to the nonuniformity of SiGe resistors, the boron ions should be implanted as many as possible. In addition, the resistance deviation increases as the size of the contact hole that interconnects the SiGe resistor and the metal line decreases. Therefore, the size of the contact hole must be enlarged in order to reduce the resistance deviation.

• The Journal of the Korea Contents Association
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• v.8 no.3
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• pp.25-31
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• 2008

We propose a low power level-up/down shifter with single supply that can be used at SoC with multiple supply. The proposed circuit interfaces IPs which are operated on the different supply voltages. The circuit is designed with a single supply that decreases the low power consumption and the complexity of supply routing and layout. The proposed circuit operated at 500MHz for level-up and at 1GHz for level-down. The level-up/down shifter improves noise immunity of the system at I/O circuit. The circuit is evaluated for 1.8V, 2.5V, 3.3V supply with 0.18um CMOS technology, respectively.