1 |
H. Bakoglu, and J. D. Meindl, "Optimal interconnection circuits for VLSI", IEEE Transactions on Electron Devices, 32(5), 903 (1985).
|
2 |
N. Shinoda, T. Shimizu, T. F. Chang, and A. Shibata, and M. Sone, "Filling of nanoscale holes with high aspect ratio by Cu electroplating using suspension of supercritical carbon dioxide in electrolyte with Cu particles", Microelectronic Engineering, 97, 126 (2012).
|
3 |
P. Vereecken, P. Binstead, H. Deligianni, and P. Andricacos, "The chemistry of additives in damascene copper plating", IBM Journal of Research and Development, 49(1), 3 (2005).
DOI
|
4 |
E. M. Zielinski, S. W. Russell, and R. S. List, A. M. Wilson, C. Jin, K. J. Newton, J. P. Lu, T. Hurd, W. Y. Hsu, V. Cordasco, M. Gopikanth, V. Korthuis, W. Lee, G. Cerny, N. M. Russell, P. B. Smith, S. O'Brien, and R. H. Havemann, "Damascene integration of copper and ultra-low-k xerogel for high performance interconnects", IEEE Electron Devices Meeting, 936 (1997).
|
5 |
K. Ueno, T. Ritzdorf, and S. Grace, "Seed layer dependence of room-temperature recrystallization in electroplated copper films", Journal of applied physics, 86(9), 4930 (1999).
DOI
|
6 |
K. Ritzdorf, L. Graham, and S. Jin, et al., "Self-annealing of electrochemically deposited copper films in advanced interconnect applications", Proc. International Interconnect Technology, 166 (1998).
|
7 |
J. M. E. Harper, C. Cabral, and Jr., P. C. Andricacos, L. Gignac, I. C. Noyan, K. P. Rodbell, and C. K. Hu, "Mechanisms for microstructure evolution in electroplated copper thin films near room temperature", Journal of applied physics, 86(5), 2516 (1999).
DOI
|
8 |
H. Lee, S. S. Wong, and S. D. Lopatin, "Correlation of stress and texture evolution during self- and thermal annealing of electroplated Cu films", Journal of applied physics, 93(7), 3796 (2003).
DOI
|
9 |
M. Stangl, J. Acker, V. Dittel, W. Gruner, V. Hoffmann, and K. Wetzig "Characterization of electroplated copper selfannealing with investigations focused on incorporated impurities," Microelectronic Engineering, 82, 189 (2005).
|
10 |
H. Lee, W. D. Nix, and S. S. Wong, "Studies of the driving force for room-temperature microstructure evolution in electroplated copper films", Journal of vacuum science & technology, 22(5), 2369 (2004).
|
11 |
S. Lagrange, S. Brongersma, M. Judelewicz, A. Saerens, I. Vervoort, E. Richard, R. Palmans, and K. Maex "Self-annealing characterization of electroplated copper films", Microelectronic Engineering, 50, 449 (2000).
|
12 |
M. Stangl, and M. Militzer "Modeling self-annealing kinetics in electroplated Cu thin films," Journal of applied physics, 103(113521), 1 (2008).
|
13 |
C. Ryu, K. W. Kwon, A. L. S. Loke, H. Lee, T. Nogami, V. M. Dubin, R. A. Kavari, G. W. Ray, and S. S. Wong, "Microstructure and reliability of copper interconnects", IEEE Trans. Electron Devices, 46(6), 1113 (1999).
|
14 |
J. Y. Cho, H. J. Lee, H. Kim, and J. A. Szpunar, "Textural and microstructural transformation of Cu damascene interconnects after annealing", Journal of Electronic materials, 34(5), 506 (2005).
DOI
|