• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.59-66
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• 2018

In this paper, we analyzed the usefulness of single-structured printed circuit board (PCB) modeling by using numerical analysis to model the PCB structure applied to a package for semiconductor purposes and applying modeling assuming a single structure. PCBs with circuit layer of 3rd and 4th were used for analysis. In addition, measurements were made on actual products to obtain material characteristics of a single structure PCB. The analysis results showed that if the PCB was modeled in a single structure compared to a multi-layered structure, the warpage analysis results resulting from modeling the PCB structure would increase and there would be a significant difference. In addition, as the circuit layer of the PCB increased, the mechanical properties of the PCB, the elastic coefficient and inertia moment of the PCB increased, decreasing the package's warpage.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.5-9
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• 2015

Thermal management becomes serious in 3D stacked IC because of higher heat flux, increased power generation, extreme hot spot, etc. In this paper, we reviewed the recent developments of thermal management for 3D stacked IC which is a promising candidate to keep Moore's law continue. According to experimental and numerical simulation results, Cu TSV affected heat dissipation in a thin chip due to its high thermal conductivity and could be used as an efficient heat dissipation path. Other parameters like bumps, gap filling material also had effects on heat transfer between stacked ICs. Thermal aware circuit design was briefly discussed as well.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.2
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• pp.53-58
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• 2020

Analysis of electric semiconductor packaging technology for electric vehicles was performed. Topic modeling using LDA technique was performed by collecting valid patents by deriving valid patents. It was classified into 20 topics, and the definition of technology was defined through extracted words for each topic. In order to analyze the trend of each topic, the trend of power semiconductor packaging technology was analyzed by deriving hot and cold topics by topic through regression analysis on frequency by year. The package structure technology according to the withstand voltage, the input/output-related control technology and the heat dissipation technology were derived as the hot topic technology, and the inductance reduction technology was derived as the cold topic technology.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.55-65
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• 2020

The use of underfill materials in semiconductor packages is not only important for stress relieving of the package, but also for improving the reliability of the package during shock and vibration. However, in recent years, as the size of the package becomes larger and very thin, the use of the underfill shows adverse effects and rather deteriorates the reliability of the package. To resolve these issues, we developed the package using a solid epoxy material to improve the reliability of the package as a substitute for underfill material. The developed solid epoxy was applied to the package of the application processor in smart phone, and the reliability of the package was evaluated using thermal cycling reliability tests and numerical analysis. In order to find the optimal solid epoxy material and process conditions for improving the reliability, the effects of various factors on the reliability, such as the application number of solid epoxy, type of PCB pad, and different solid epoxy materials, were investigated. The reliability test results indicated that the package with solid epoxy exhibited higher reliability than that without solid epoxy. The application of solid epoxy at six locations showed higher reliability than that of solid epoxy at four locations indicating that the solid epoxy plays a role in relieving stress of the package, thereby improving the reliability of the package. For the different types of PCB pad, NSMD (non-solder mask defined) pad showed higher reliability than the SMD (solder mask defined) pad. This is because the application of the NSMD pad is more advantageous in terms of thermomechanical stress reliability because the solderpad bond area is larger. In addition, for the different solid epoxy materials with different thermal expansion coefficients, the reliability was more improved when solid epoxy having lower thermal expansion coefficient was used.

• JOURNAL OF ELECTRICAL WORLD
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• s.323
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• pp.69-75
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• 2003

불투명한 경제정세의 와중에서도 전기에너지를 지탱하는 근간이 되는 파워 일렉트로닉스 분야는 확실히 그 기술개발을 향상시켜 오고 있다. 특히 파워디바이스는, 지구환경과 생활환경을 보다 쾌적하게 하기 위하여 인버터 장치 등의 각종 전력절약기기와 풍력$\cdot$태양광$\cdot$연료전지 등 클린에너지의 전력제어장치에 없어서는 안되는 반도체디바이스로 성장했다. 파워디바이스 중에서도 IGBT(Insulated Gate Bipolar Transistor)의 기술혁신은 요 20년 사이에 비약적인 성과를 거두었다. 1980년대에 제품화된 IGBT는, 반도체메모리의 초미세가공기술을 도입하면서 $5{\mu}m$에서 서브미크론의 디자인툴로 발전하여, 2000년대에 들어 칩의 전류밀도는 약 2배, 포화전압은 약 $65\%$까지 개량되었다. 이와 같은 IGBT의 변천은, 전력손실을 대폭적으로 저감시켜 에너지절약기기의 전력변환효율 향상에 공헌하고 있다. 파워디바이스의 기술진보에서 또 한 가지 잊지 말아야 할 것은 주변회로의 집적화(集積化)에 의한 고성능$\cdot$고기능화이다. 최근의 인버터용 파워디바이스로 가장 많이 사용되고 있는 파워모듈은, IGBT등의 파워칩과 그 주변회로와의 컬래버레이션에 의한 제품이다. 다시 말하면 구동회로, 전류$\cdot$전압$\cdot$온도센서 및 그것들의 보호회로가 IC(집적회로)에 편입되어 고기능$\cdot$소형화를 촉진시키고 있다. 구동회로는 LVIC (저전압집적회로)에서 HVIC(고전압집적회로)로 발전하여 전류$\cdot$온도 등의 각종 센서도 동일 칩에 설계할 수 있게 되었다. 또 센싱이나 보호기능뿐만이 아니라 출력전류의 제어를 위한 연산기능과 di/dt의 제어기능이 내장되도록 되어 있어 보다. 고성능의 인텔리전트 파워모듈(IPM)이라고 불리우는 새로운 개념의 파워디바이스가 실현되었다. 또한 패키지 기술도 내부배선 인덕턴스의 저감과 트랜스퍼 몰드패키지의 개발로, 소형화뿐만이 아니라 파워칩의 성능$\cdot$기능을 충분히 발휘할 수 있도록 개발이 적극적으로 추진되고 있다.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.89-93
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• 2020

Complex warpage behavior of the electronic packages causes internal stress so many kinds of mechanical failure occur such as delamination or crack. Efforts to predict the warpage behavior accurately in order to prevent the decrease in yield have been approached from various aspects. For warpage prediction, silicon is generally treated as a homogeneous material, therefore it is described as showing no warpage behavior due to thermal loading. However, it was reported that warpage is actually caused by residual stress accumulated during grinding and polishing in order to make silicon wafer thinner, which make silicon wafer inhomogeneous through thickness direction. In this paper, warpage behavior of the single-side polished wafer at solder reflow temperature, the highest temperature in packaging processes, was measured using 3D digital image correlation (DIC) method. Mechanism was verified by measuring coefficient of thermal expansion (CTE) of both mirror-polished surface and rough surface.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.37 no.1
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• pp.75-79
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• 2013

Demands for semiconductor devices are dramatically increasing, and advancements in fabrication technology are allowing a step-up in the number of devices per unit area. As a result, semiconductor devices require higher heat dissipation, and thus, cooling solutions have become important for guaranteeing their operational reliability. In particular, in chip-in-board packages, in which chips and passives are embedded in the substrates for efficient device layout, heat dissipation is of greater importance. In this study, a thermal model for layers of different materials has been proposed, and then, the heat transfer has been simulated by imposing a set of appropriate boundary conditions. Heat generation can be predicted based on the results, which will be utilized as practical data for actual package design.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.23-31
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• 2019

In this study, we conducted numerical analyses using the Taguchi method and finite element method to calculate the thermal deformation of a printed circuit board and the effect of design factors on the thermal deformation. Analysis results showed that the thermal deformation of the panel had the strongest effect on the thermal deformation and shape of the strip and unit. In particular, the deformation in the z direction was larger than that in the xy-plane direction. The effect of design factors and the design conditions for reducing the thermal deformation of the panel and strip changed at the unit level. Therefore, it is recommended that panel-level thermal deformation must be controlled to reduce the final thermal deformation at the unit level because the thermal deformation of the strip strongly affects that of the unit.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.2
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• pp.120-126
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• 2009

There are many different types of surface defects on semiconductor Integrated Chips (IC's) caused by various factors during manufacturing process, such as cracks, foreign materials, chip-outs, chips, and voids. These defects must be detected and classified by an inspection system for productivity improvement and effective process control. Among defects, in particular, foreign materials and chips are the most difficult ones to classify accurately. A vision system composed of a carefully designed optical system and a processing algorithm is proposed to detect and classify the defects on QFN(Quad Flat No-leads) packages. The processing algorithm uses features derived from the defect's position and brightness value in the Maximum Likelihood classifier and the optical system is designed to effectively extract the features used in the classifier. In experiments we confirm that this method gives more effective result in classifying foreign materials and chips.

• Journal of the Korea Convergence Society
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• v.9 no.11
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• pp.9-14
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• 2018

The vision system is a device for acquiring images and analyzing and discriminating inspection areas. Demand for use in the automation process has increased, and the introduction of a vision-based inspection system has emerged as a very important issue. These vision systems are used for everyday life and used as inspection equipment in production processes. Image processing technology is actively being studied. However, there is little research on the area definition for extracting objects such as character recognition or semiconductor packages. In this paper, define a region of interest and perform edge extraction to prevent the user from judging noise as an edge. We propose a noise-robust alignment correction model that can extract the edge of a region to be inspected using the distribution of edges in a specific region even if noise exists in the image. Through the proposed model, it is expected that the product production efficiency will be improved if it is applied to production field such as character recognition of tire or inspection of semiconductor packages.