• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.876-877
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• 2014

In recently, the SNS which is the hot issue of the knowledge-based information age use various goal based on human networking. This service construct a human relationship which exchange of information and opinion freely, and can extend the human network relationship using open his profile and closeness others. But, each individual's privacy invasions and pissing based on information open and sharing are rising. In this paper we present a method of protecting the SNS group's communications and information interchangeability efficiently.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.768-769
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• 2016

To prevent occupational disasters and build a pleasant work environment, it is necessary to develop a monitoring system to keep operators safe from the hazards. A variety of practical studies must be performed on application services designed to freely provide context-aware monitoring services in USN environments. This paper proposes a system in which work environment monitoring information can be monitored using a mobile phone and inference engine. The structure of a mobile work environment monitoring system is designed first. The proposed system is consisted of data manager, inference engine, database, and application knowledge base.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.558-560
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• 2019

Recently, there are steadily required more highly broadcasting service based on the broadcasting extension and improved quality. This paper proposed the method of the implemented above mentioned. The proposed high speed data link techniques method is more improved processing speed and more efficiently editing advantage compare with earlier methods.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.295-308
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• 1986

This paper presents a method of constructing multiple-valued logic functions based on Galois field. The proposed algorithm assigns all elements in GF(2**m) to bit codes that are easily converted binary. We have constructed an adder and a multiplier using a multiplexer after bit code operation (addition, multiplication) that is performed among elements on GF(2**m) obtained from the algorithm. In constructing a generalized multiple-valued logic functions, states are first minimized with a state-transition diagram, and then the circuits using PLA widely used in VLSI design for single and multiple input-output are realized.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.41-45
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• 2017

This paper presents a method of constructing the efficiency multiple output switching function of the combinational logic systems. The proposed method reduce the optimized input variable pair and output variable pair after we obtained the final multiple output switching function which was time based multiplexing and obtained the common multiple end node extension logic decision diagram. Also the proposed method have an advantage of the cost, input-output node number, circuit simplification, increment of the arithmetic speed, and more regularity and extensibility compare with previous method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.12
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• pp.2187-2192
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• 2006

This paper presents a method of constructing the universal multiple processing element unit(UMPEU) by De Bruijn Graph. The second method is as following. First, we propose transformation operators in order to construct the De Bruijn UMPEU using properties of graph. Second, we construct the transformation table of De Bruijn graph using above transformation operators. Finally we construct the De Bruijn graph using transformation table. The proposed UMPEU be able to construct the De Bruijn graph for any prime number and integer value of finite fields. Also the UMPEU is applied to fault-tolerant computing system, pipeline class. parallel processing network, switching function and its circuits.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1965-1970
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• 2011

This paper proposes the method of switching function implementation using switching function extraction based on graph over finite fields. After we deduce the matrix equation from path number of directional graph, we propose the switching function circuit algorithm, also we propose the code assignment algorithm for nodes which is satisfied the directional graph characteristics with designed circuits. We can implement more optimal switching function compare with former algorithm, also we can design the switching function circuit which have any natural number path through the proposed switching function circuit implementation algorithms. Also the proposed switching function implementation using graph theory over finite fields have decrement number of input-output, circuit construction simplification, increment arithmetic speed and decrement cost etc.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.9
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• pp.2091-2096
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• 2013

This paper present a method of efficiency circuit design based on directed graph which was represented by tree structure relationship between input and output of nodes. In this paper, we introduce the concept of mathematical analysis based on tree structure which was designed by optimal localized computable circuit. Using the proposed circuit design algorithms in this paper, it is possible to design circuit which directed tree graph have any node number. The proposed method is more effective, regularity and extensibility than former method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.470-471
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• 2018

This paper presents a design method for combinational digital logic systems using time domain based multiplexing and common multi-terminal extension decision diagrams. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.769-770
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• 2011

This paper presented a method constructing the ITSoC(Information Technology System-on-Chip). In order to implement the ITSoC, designers are increasing relying on reuse of intellectual property(IP) blocks. Since IP blocks are pre-designed and pre-verified, the designer can concentrate on the complete system without having to worry about the correctness or performance of the individual components. Also, embedded core in an ITSoC access mechanisms are required to test them at the system level. That is the goal, in theory. In practice, assembling an ITSoC using IP blocks is still an error-prone, labor-intensive and time-consuming process. This paper discuss the main challenge in ITSoC designs using IP blocks and elaborates on the methodology and tools being put in place for addressing the problem. It explains ITSoC architecture and gives algorithmic details on the high-level tools being developed for ITSoC design.