• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.39 no.2
• /
• pp.29-33
• /
• 2002

Various nanometer-scale structures are fabricated on hydrogen-passivated p-type Si(100) surface by scanning probe microscopy(SPM). The hydrogen-passivation is performed by dipping the samples in diluted 10% HF solution for one min.. Pt alloy wires are used for tips and the tips are made by cutting the wires at 45$^{\circ}$ slanted. Various line features are fabricated in various bias voltage. The optimal structure is the line of about 30 nm width on 1.7V bias voltage and 1 nA tunneling current.  

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.14 no.3
• /
• pp.18-24
• /
• 1977

In this paper, a series inverter circuit is constructed by using the pinch-off characteristics of FET, and itsoutput characteristics is analysed for the variation of gate bias frequency and load. The above constructed circuit could eliminate the unstable output characteristics of SCR-series inverter fir chit by the changes of gate bias frequency and load resistor. But the current capacity of the FET-series inverter circuit is relatively small, and is recommended to be used for light loads.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2002.05a
• /
• pp.158-164
• /
• 2002

본 연구에서는 탄소나노튜브를 직류 바이어스가 인가된 유도결합형 플라즈마 열선 화학기상증착 장치를 이용하여 58$0^{\circ}C$ 이하의 저온에서 유리기판의 변형 없이 수직 배향 시켰다. 탄소나노튜브의 성장을 위해 강화유리기판 위에 전도층으로 Cr을 증착하였고, 그 위에 촉매 층으로 Ni을 순차적으로 RF magnetron cputtering 장치를 이용하여 증착 시켰다. 성장 시 탄소나노튜브의 저온에서의 좋은 특성을 위해 높은 온도에서의 열분해를 목적으로 텅스텐 필라멘트를 이용하였으며, 수직 배향 시키기 위해서 직류 바이어스를 이용하였다. 성장된 탄소나노튜브는 수직적으로 잘 배향 되었으며, 저온에서 좋은 특성을 보였다. 탄소나노튜브의 특성화에는 SEM, TEM을 관찰하였으며, Raman spectroscopy를 이용하여 흑연화도를 측정하였고, 전계방츨 특성은 전류 전압 특성곡선과 Fowler-Nordheim plots를 이용하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.12 no.1
• /
• pp.65-70
• /
• 2001

This paper presents a Receiver MMIC for the CDMA terminal. The complete circuit is composed of Low Noise Amplifier, Down Conversion Mixer, Intermediate Frequency Amplifier and Bias circuit. The Bias circuit implementation, which allows for compensation for threshold voltage and power supply voltage variation are provided. The proposed topology has high linearity and low noise characteristics. Results of the designed circuit are as follows: Overall conversion gain is 28.5 dB, input IP3 of LNA is 8 dBm, input IP3 of down conversion mixer is 0 dBm and total DC current consumption is 22.1 mA.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.2
• /
• pp.316-321
• /
• 2005

A new HBT current source model and the corresponding direct parameter extraction methods are presented. Exact analytical expressions for the current source model parameters are derived. This method is applied to scalable modeling of HBT, Some techniques to reduce redundancy of the parameters are introduced. The model based on this method can accurately predict the measured data for the change of ambient temperature, size, and bias.

• Korean Journal of Materials Research
• /
• v.8 no.1
• /
• pp.10-12
• /
• 1998

Si FEA 로부터 tip의 표면을 Ti금속으로 silicidation한 새로운 2극형 Ti-실리사이드 FEA를 제작하고 이의 전계방출 특성을 Si FEA의 경우와 비교하였다. 양극과 음극간의 거리를 10$\mu\textrm{m}$로 유지하고 $10^{-8}$Torr의 고진공 상태에서 측정한 실리사이드 FEA의 turn-on전압은 약 40V로, 전계방출전류와 정상상태 전류 변동율은 150V의 바이어스 아래에서 약 3x$10^{-2}$ $\mu$A/tip와 0.1%min로 나타났다. Ti-실리사이드 FEA는 Si FEA에 비해 낮은 turn-on 전압, 높은 전계방출전류 및 고내구특성을 나타내었다.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.17 no.2
• /
• pp.10-14
• /
• 1980

In this paper, the second harmonic distortion of the DH L.D. is analyzed using dynamic and static rate equations. In this analysis the modulation current Jm is changed by varang the iinjection current with the relation of where m stands for modulation index. It is showed that relative harmonic distortion ( ) has a peak exactly at the threshold current. It is also confirmed that this method is simople and more accurate than previously reported methods in the decision of the threshold current.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.195-195
• /
• 2011

플라즈마를 이용한 반도체 이온 주입 공정(Plasma Immersion Ion Implantation)에서 이온 도즈량(DOSE) 측정은 공정 신뢰성 및 재현성 확보를 위해 중요하다. 본 연구에서는 도즈량 측정을 위해 패러데이컵과 같이 측정 장비를 챔버에 직접 삽입 시키지 않고 챔버 외부에서 이온 주입을 위한 바이어스 전극의 직류 펄스 전압 및 전류 신호 측정을 통해 실시간으로 도즈량을 추출하는 방법을 개발하였다. 펄스 전압 신호에서 전압 신호 상승, 하강 시간에 의해 발생된 변위 전류와 플라즈마 발생 소스의 RF잡음등을 제거한 후 이온 포격으로 인한 2차 전자 방출 계수를 고려하여 펄스 동작 기간 추출을 통해 실시간으로 측정하는 알고리즘을 구현하였다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.5B
• /
• pp.974-984
• /
• 2000

A CMOS voltage driver circuit for voltage down converter is proposed. An adaptive biasing technique is used to enhance load regulation characteristics. The proposed driver circuit uses the NMOS transistor as a driving transistor, so it does not suffer from large Miller capacitances which is one of the problems with conventional PMOS driving transistor, and hence achieves good phase margin and stable frequency response. No additional complex circuit for frequency compensation such as compensation capacitor is required in this implementation. For the same current capability, the size of NMOS transistor in driver circuit is smaller than that of PMOS counterpart. So the smaller die area can be achieved. The circuits is implemented using a 0.8 ${\mu}{\textrm}{m}$ CMOS process and has a die area of 150 ${\mu}{\textrm}{m}$ x 360 ${\mu}{\textrm}{m}$. Proposed circuit has a quiescent power of 60 . In the current driving range from 100 $mutextrm{A}$ to 50 ㎃, load regulation of 5.6 ㎷ is measured.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.1-7
• /
• 2006

An on chip voltage down converter (VDC) using the self temperature-compensation techniques is proposed. At a different gate bias voltage, PMOSFET shows different source to drain current characteristic according to the temperature variation. The proposed VDC can reduce its temperature dependency by the source to drain current ratio of two PMOSFET with different gate bias respectively. Proposed circuit is fabricated in Dongbu-anam $0.18{\mu}m$ CMOS process and experimental results show its temperature dependency of $-0.49mV/^{\circ}C$ and external supply dependency of 6mV/V. Total current consumption is only $1.1{\mu}A@2.5V$.