• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.45-51
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• 2001

The effects of wettability and surface oxidation on the low temperature and ultra-fine solder bump formation have been studied. Difference sequences of near eutectic In-Ag and eutectic Bi-Sn solders were evaporated on Au/Cu/Cr or Au/Ni/Ti Under Bump Metallurgy (UBM) pads. Solder bumps were formed using lift-off method and were reflowed in Rapid Thermal Annealing (RTA) system. The solder bumps in which In was in contact with UBM in In-Ag solder and the solder bumps in which Sn was in contact with UBM in Bi-Sn solder showed better bump formability during reflow than other solder bumps. The ability to form spherical solder bumps was affected mainly by the wettability of solders to UBM pads.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.122-127
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• 2003

본 논문에서는 새로운 솔더 범프 형성 방법 중의 하나인 Solder droplet jetting에 의한 솔더 범프 형성 공정에 대해 연구하였으며, 이를 위해 솔더 제팅 직후의 안정한 솔더 액적(solder droplets)의 형성을 위한 공정 변수들의 영향에 대해 먼저 알아보았다 이를 위해 제팅 노즐에 가해지는 파형과 용융 솔더의 온도, 질소 가스의 압력 등에 의한 영향을 주로 살펴보았다. 다음으로 리플로를 거쳐 솔더 범프를 형성하였으며, 다양한 크기의 솔더 범프를 간단한 방법으로 형성하였다. 또한 무전해 니켈/솔더 계면 반응과 Bump shear test를 통한 기계적 성질을 고찰하는 한편, 계면 반응 결과는 스크린 프린팅에 의해 형성된 솔더 범프의 결과와 비교함으로써, 저가의 공정으로 미세 피치를 갖는 솔더 범프를 형성할 수 있는 Solder droplet jetting 방법이 기존의 방법에 의해 형성된 솔더 범프의 특성과 유사함을 고찰하였다. 마지막으로 실제 칩에 적용 되는 솔더 범프를 형성하여 플립칩 어셈블리 및 전기적 테스트를 수행하여, Solder droplet jetting이 실제 차세대 플립칩용 솔더 범프 형성 방법으로서 적용될 수 있음을 고찰하였다.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.45-51
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• 2013

Thermal annealing tests were performed in an in-situ scanning electron microscope chamber at $130^{\circ}C$, $150^{\circ}C$, and $170^{\circ}C$ in order to investigate the effects of solder structure on the growth kinetics of intermetallic compound (IMC) in Cu/Sn-3.5Ag microbump. Cu/Sn-3.5Ag($6{\mu}m$) microbump with spreading solder structure showed $Cu_6Sn_5$ and $Cu_3Sn$ phase growths and then IMC phase transition stages with increasing annealing time. By the way, Cu/Sn-3.5Ag($4{\mu}m$) microbump without solder spreading, remaining solder was transformed to $Cu_6Sn_5$ right after bonding and had only a phase transition of $Cu_6Sn_5$ to $Cu_3Sn$ during annealing. Measured activation energies for the growth of the $Cu_3Sn$ phase during the annealing were 0.80 and 0.71eV for Cu/Sn-3.5Ag($6{\mu}m$) and Cu/Sn-3.5Ag($4{\mu}m$), respectively.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.49-56
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• 2012

Recently, by the trends of electronic package to be smaller, thinner and more integrative, fine bump is required. but It can result in the electrical short by reduced cross-section of UBM and diameter of bump. Especially, the formation of IMCs and KV can have a significant affects about electrical and mechanical properties. In this paper, we analyzed the thermal deformation of flip-chip bump by using FEM. Through Thermal Cycling Test (TCT) of flip-chip package, We analyzed the properties of the thermal deformation. and We confirmed that the thermal deformation of the bump can have a significant impact on the driving system. So we selected IMCs thickness and bump diameter as variable which is expected to have implications for characteristics of thermal deformation. and we performed analysis of temperature, thermal stress and thermal deformation. Then we investigated the cause of the IMC's effects.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.83-88
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• 2018

The electromigration (EM) tests were performed at $150^{\circ}C$ with $1.5{\times}10^5A/cm^2$ conditions in order to investigate the effect of non-conductive film (NCF) trap on the electrical reliability of Cu/Ni/Sn-Ag microbumps. The EM failure time of Cu/Ni/Sn-Ag microbump with NCF trap was around 8 times shorter than Cu/Ni/Sn-Ag microbump without NCF trap. From systematic analysis on the electrical resistance and failed interfaces, the trapped NCF-induced voids at the Sn-Ag/Ni-Sn intermetallic compound interface lead to faster EM void growth and earlier open failure.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.41 no.6
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• pp.443-453
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• 2017

In flip chip technology, the conventional solder bump has been replaced with a copper (Cu) pillar bump owing to its higher input/output (I/O) density, finer pitch, and higher reliability. However, Cu pillar bump technology faces several issues, such as interconnect shorting and higher low-k stress due to stiffer Cu pillar structure when the conventional reflow process is used. Therefore, the thermal compression bonding (TCB) process has been adopted in the flip chip attachment process in order to reduce the package warpage and stress. In this study, we investigated the package warpage induced during the TCB process using a numerical analysis. The warpage of the TCB process was compared with that of the reflow process.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.9-15
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• 2009

Compared to the flip-chip process using solder bumps, Cu pillar bump technology can accomplish much finer pitch without compromising stand-off height. Flip-chip process with Cu pillar bumps can also be utilized in radio-frequency packages where large gap between a chip and a substrate as well as fine pitch interconnection is required. In this study, Cu pillars with and without Sn caps were electrodeposited and flip-chip-bonded together to form the Cu-Sn-Cu sandwiched joints. Contact resistances and die shear forces of the Cu-Sn-Cu sandwiched joints were evaluated with variation of the height of the Sn cap electrodeposited on the Cu pillar bump. The Cu-Sn-Cu sandwiched joints, formed with Cu pillar bumps of $25-{\mu}m$ diameter and $20-{\mu}m$ height, exhibited the gap distance of $44{\mu}m$ between the chip and the substrate and the average contact resistance of $14\;m{\Omega}$/bump without depending on the Sn cap height between 10 to $25\;{\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.67-73
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• 2009

Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2013.05a
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• pp.56-56
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• 2013

Sn-Ag 전해도금시 도금욕의 Sn 이온의 농도, Ag 이온의 농도, MSA 함량 및 인가 전류밀도 등의 인자들이 솔더의 조성과 표면형상에 미치는 영향에 관하여 연구하였다. 본 연구를 통하여 20의 미세피치와 15의 범프 높이를 가지는 공정 Sn-Ag 솔더 범프를 형성하였다. 도금된 솔더의 조성은 XRF와 ICP 분석을 통하여 확인하였고 형상은 광학현미경과 SEM을 통해 분석하였다. 또한 void 발생 여부 확인을 위해 FIB장비 및 X-Ray inspection장비를 사용 내부 Void 형상을 분석하였다. 전해 도금시 작용하는 주요 도금인자의 변경을 통해 15ASD에서 양호한 Bump를 구현하였다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2014.11a
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• pp.136-137
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• 2014

주석계 전기도금액에 포함된 불소계 계면활성제는 분산 유화 소포 효과를 발휘할 수 있으며, 도금 금속 결정을 미세하게 하여 범프의 그레인 크기와 모양 특성을 개선하며, 범프의 높이 차 (WID, WIW) 감소 및 범프 내 빈 공간과 금속간 층의 균열 생성 방지에 영향을 주었음을 알 수 있었다.