• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.839-841
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• 2015

본 연구에서는 비대칭 이중게이트 MOSFET의 채널길이와 채널두께의 비에 따른 드레인 유도 장벽 감소 현상의 변화에 대하여 분석하고자한다. 드레인 전압이 소스 측 전위장벽에 영향을 미칠 정도로 단채널을 갖는 MOSFET에서 발생하는 중요한 이차효과인 드레인 유도 장벽 감소는 문턱전압의 이동 등 트랜지스터 특성에 심각한 영향을 미친다. 드레인 유도 장벽 감소현상을 분석하기 위하여 포아송방정식으로부터 급수형태의 전위분포를 유도하였으며 차단전류가 $10^{-7}A/m$일 경우 비대칭 이중게이트 MOSFET의 상단게이트 전압을 문턱전압으로 정의하였다. 비대칭 이중게이트 MOSFET는 단채널효과를 감소시키면서 채널길이 및 채널두께를 초소형화할 수 있는 장점이 있으므로 본 연구에서는 채널길이와 두께 비에 따라 드레인 유도 장벽 감소를 관찰하였다. 결과적으로 드레인 유도 장벽 감소 현상은 단채널에서 크게 나타났으며 하단게이트 전압, 상하단 게이트 산화막 두께 그리고 채널도핑 농도 등에 따라 큰 영향을 받고 있다는 것을 알 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.333.2-333.2
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• 2014

RF 스퍼터링 방법을 이용하여 제작된 IGZO 박막 트랜지스터 및 단막을 제조하여 UV처리 유무에 따른 전기적 특성을 평가하였다. IGZO 박막 트랜지스터는 Bottom gate 구조로 제조되었으며 UV처리 이후 전계효과 이동도, 문턱전압 이하 기울기 값등 모든 전기적 특성이 개선된 것을 확인 하였다. 이후 UV처리에 따른 소자의 전기적 특성 개선에 대한 원인을 분석하기위해 물리적, 전기적, 광학적 분석을 실시하였다. XRD분석을 통해 UV처리 유무에 따른 IGZO박막의 물리적 구조 변화를 관찰했지만 IGZO박막은 UV처리 유무에 상관없이 물리적 구조를 갖지 않는 비정질 상태를 보였다. IGZO 박막 트랜지스터의 문턱전압 이하의 기울기 값과을 통하여 반도체 내부에 존재하는 결함의 양을 계산한 결과 UV를 조사하였을 때 결함의 양이 감소하는 결과를 얻었으며 이 결과는 SE를 통해 밴드갭 이하 결함부분을 측정하였을 때와 같은 결과였다. 또한 UV처리 전에는 shallow level defect, deep level defect등의 넓은 준위에서 결함이 발견된 반면 UV처리 이후에는 deep level defect준위는 없어지고 shallow level defect준위 역시 급격하게 감소한 것을 볼 수 있었다. 결과적으로 IGZO 박막의 경우 UV처리를 함에 따라 결함의 양이 감소하여 IGZO박막 트랜지스터의 전계 효과 이동도를 증가 시킬 뿐 아니라 문턱전압 이하 기울기 값을 감소시키는 원인으로 작용하게 된다는 결과를 도출하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.664-667
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• 2011

In this paper, threshold voltage characteristics have been analyzed as one of short channel effects occurred in double gate(DG)MOSFET to be next-generation devices. The Gaussian function to be nearly experimental distribution has been used as carrier distribution to solve Poisson's equation, and threshold voltage has been investigated according to projected range and standard projected deviation, variables of Gaussian function. The analytical potential distribution model has been derived from Poisson's equation, and threshold voltage has been obtained from this model. Since threshold voltage has been defined as gate voltage when surface potential is twice of Fermi potential, threshold voltage has been derived from analytical model of surface potential. Those results of this potential model are compared with those of numerical simulation to verify this model. As a result, since potential model presented in this paper is good agreement with numerical model, the threshold voltage characteristics have been considered according to the doping profile of DGMOSFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.981-984
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• 2005

This study is to realize its threshold voltage shift after programming operation in charge trap type SONOS memory by simulation. SONOS devices are charge trap type nonvolatile memory devices in which charge storage takes place in traps in the nitride-blocking oxide interface and the nitride layer. For simulation of their threshold voltage as a function of the memory states, traps in the nitride layer have to be defined. However, trap models in the nitride layer are not developed in commercial simulator. So, we propose a new method that can simulate their threshold voltage shift by an amount of charges induced to the electrodes as a function of a programming voltages and times as define two electrodes in the tunnel oxide-nitride interface and the nitride-blocking oxide interface of SONOS structures.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.769-772
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• 2014

The device reliability in amorphous InGaZnO under NBS(Negative Bias Stress) and hot carrier stress with different gate overlap has been characterized. Amorphous InGaZnO thin film transistor has been measured. and is channel $width=104{\mu}m$, $length=10{\mu}m$ with gate overlap $length=0,1,2,3{\mu}m$. The device reliability has been analyzed by I-V characteristics. From the experiment results, threshold voltage variation has been increased with increasing of the gate overlap length after hot carrier stress. Also, threshold voltage variation has been decreased and Hump Effect has been observed later with increasing of the gate overlap length after NBS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1764-1770
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• 2011

In this paper, the subthreshold swings for doping distribution in the channel have been analyzed in double gate MOSFET(DGMOSFET). The DGMOSFET is extensively been studying since it can lessen the short channel effects(SCEs) as next -generation nano device. The degradation of subthreshold swing(SS) known as SCEs has greatly influenced on application of digital devices, and has been analyzed for structural parameter and variation of channel doping profile in DGMOSFET. The analytical model of Poisson equation has been derived from nonuniform doping distribution for DGMOSFET. To verify potential and subthreshold swing model based on this analytical Poisson's equation, the results have been compared with those of the numerical Poisson's equation, and subthreshold swing for DGMOSFET has been analyzed using these models.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1925-1930
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• 2014

This paper has analyzed the relation of conduction path and subthreshold swing for doping profile in channel of asymmetric double gate(DG) MOSFET. Since the channel size of asymmetric DGMOSFET is greatly small and number of impurity is few, the high doping channel is analyzed. The analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. The conduction path and subthreshold swing are derived from this analytical potential distribution, and those are investigated for variables of doping profile, projected range and standard projected deviation, according to the change of channel length and thickness. As a result, subthreshold swing is reduced when conduction path is approaching to top gate, and that is increased with a decrease of channel length and a increase of channel thickness due to short channel effects.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.1-6
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• 2008

A compact analytical model of the threshold voltage for long-channel Asymmetric Double-Gate(ADG) MOSFET is presented. In contrast to the previous models, channel doping and carrier quantization are taken into account. A more compact model is derived by utilizing the potential distribution linearity characteristic of silicon film at threshold. The accuracy of the model is verified by comparisons with numerical simulations for various silicon film thickness, channel doping concentration and oxide thickness.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.16-23
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• 2007

For a fully depleted SOI type symmetric double gate MOSFET, a simple expression for the threshold voltage has been derived in a closed-form To solve analytically the 2D Poisson's equation in a silicon body, the two-dimensional potential distribution is assumed approximately as a polynomial of fourth-order of x, vertical coordinate perpendicular to the silicon channel. From the derived expression for the surface potential, the threshold voltage can be obtained as a simple closed-form. Simulation result shows that the threshold voltage is exponentially dependent on channel length for the range of channel length up to $0.01\;[{\mu}m]$.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.6
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• pp.21-27
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• 1998

Electrical and optical characteristics of ZnS:Mn/ZnS:Tb multilayer TFEL devices were investigated for multi-color electroluminescent display applications. Emission spectra of M $n^{2+}$ and T $b^{3+}$ ions were observed from ZnS:Mn/ZnS:Tb multi-layer TFEL devices, and were very broad from 540 nm to 640 nm. Saturation luminance measured at 155 V was 1025 Cd/$m^2$. C-V, $Q_{t}$ - $V_{p}$ curves showed that the phosphor capacitance ( $C_{p}$ ) and the insulator capacitance ( $C_{i}$ ) were 13.5nF/$\textrm{cm}^2$ and 60 nF/$\textrm{cm}^2$, respectively. Threshold voltage( $V_{thl}$) was shown to decrease from 126 V to 93 V due to the increase of the applied voltage from 155 V to 185 V, which was attributed to the increase of the polarization charge. The equation for the calculation of the threshold voltage as a function of the applied voltage was proposed for the first time. The calculated threshold voltage agreed well with the data obtained from the measurement.t.t.t.