• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.447-457
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• 2004

This paper proposes a RSA crypto-processor for embedded systems. The architecture of the RSA crypto-processor should be used relying on Big Montgomery algorithm, and is supported by configurable bit size. The RSA crypto-processor includes a RSA control signal generator, an optimal Big Montgomery processor(adder, multiplier). We use diverse arithmetic unit (adder, multiplier) algorithm. After we compared the various results, we selected the optimal arithmetic unit which can be connected with ARM core-processor. The RSA crypto-processor was implemented with Verilog HDL with top-down methodology, and it was verified by C language and Cadence Verilog-XL. The verified models were synthesized with a Hynix 0.25${\mu}{\textrm}{m}$, CMOS standard cell library while using Synopsys Design Compiler. The RSA crypto-processor can operate at a clock speed of 51 MHz in this worst case conditions of 2.7V, 10$0^{\circ}C$ and has about 36,639 gates.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.6
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• pp.29-39
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• 2007

RSA is one of the most popular public-key crypto-system in various applications. This paper addresses a high-speed RSA crypto-processor with modified radix-4 modular multiplication algorithm and Chinese Remainder Theorem(CRT) using Carry Save Adder(CSA). Our design takes 0.84M clock cycles for a 1024-bit modular exponentiation and 0.25M cycles for a 512-bit exponentiations. With 0.18um standard cell library, the processor achieves 365Kbps for a 1024-bit exponentiation and 1,233Kbps for two 512-bit exponentiations at a 300MHz clock rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.169-170
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• 2018

이진체 상의 타원곡선 B-233을 지원하는 타원곡선 암호 프로세서를 32-비트 워드기반 몽고메리 곱셈기를 이용하여 설계하였다. 스칼라 곱셈을 위해 수정된 몽고메리 래더 (Modified montgomery ladder) 알고리즘을 적용하여 단순 전력분석에 내성을 갖도록 하였으며, Lopez-Dahab 투영 좌표계와 페르마의 소정리(Fermat's little theorem)를 적용하여 하드웨어 자원 소모가 큰 나눗셈과 역원 연산을 제거하여 저면적으로 설계하였다. 설계된 ECC 프로세서는 Xilinx ISim을 이용하여 기능검증을 하였으며, $0.18{\mu}m$ CMOS 셀 라이브러리로 합성한 결과 100 MHz의 동작 주파수에서 9,614 GEs와 4 Kbit RAM으로 구현되었으며, 최대 동작 주파수는 125 MHz로 예측되었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1471-1479
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• 2017

This paper describes a design of RSA public-key cryptography processor supporting key length of 2,048 bits. A modular multiplier that is core arithmetic function in RSA cryptography was designed using word-based Montgomery multiplication algorithm, and a modular exponentiation was implemented by using Left-to-Right (LR) binary exponentiation algorithm. A computation of a modular multiplication takes 8,386 clock cycles, and RSA encryption and decryption requires 185,724 and 25,561,076 clock cycles, respectively. The RSA processor was verified by FPGA implementation using Virtex5 device. The RSA cryptographic processor synthesized with 100 MHz clock frequency using a 0.18 um CMOS cell library occupies 12,540 gate equivalents (GEs) and 12 kbits memory. It was estimated that the RSA processor can operate up to 165 MHz, and the estimated time for RSA encryption and decryption operations are 1.12 ms and 154.91 ms, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.6
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• pp.736-743
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• 2020

Modular multiplication is one of the most important arithmetic operations in public-key cryptography such as elliptic curve cryptography (ECC) and RSA, and the performance of modular multiplier is a key factor influencing the performance of public-key cryptographic hardware. An efficient hardware implementation of word-based Montgomery modular multiplication algorithm is described in this paper. Our modular multiplier was designed to support eleven field sizes for prime field GF(p) and binary field GF(2k) as defined by SEC2 standard for ECC, making it suitable for lightweight hardware implementations of ECC processors. The proposed architecture employs pipeline scheme between the partial product generation and addition operation and the modular reduction operation to reduce the clock cycles required to compute modular multiplication by 50%. The hardware operation of our modular multiplier was demonstrated by FPGA verification. When synthesized with a 65-nm CMOS cell library, it was realized with 33,635 gate equivalents, and the maximum operating clock frequency was estimated at 147 MHz.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10a
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• pp.590-592
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• 2000

Operator-level optimization of a systolic array for Montgomery Modular Multiplication(MMM) algorithm is presented in thin paper. The proposed systolic array is faster than that of C.D. Walter by 40%. Compared with J.B. Shin et al.'s, it is 25% faster.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.3
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• pp.217-223
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• 2009

Recently, the development of the various network method can generate serious social problems. So, it is highly required to control security of network. These problems related security will be developed and keep up to confront with anti-security field such as hacking, cracking. The way to preserve security from hacker or cracker without developing new cryptographic algorithm is keeping the state of anti-cryptanalysis in a prescribed time by means of extending key-length. In this paper, the proposed montgomery multiplication structured unit array method in carry generated part and variable length multiplication for eliminating bottle neck effect with the RSA cryptosystem. Therefore, this proposed montgomery multiplier enforce the real time processing and prevent outer cracking.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.4
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• pp.223-230
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• 2006

The method of implementing a modular multiplier for Montgomery multiplication by using an adder depends on a selected adder. When using a CPA, there is a carry propagation problem. When using a CSA, it needs an additional calculation for a final result. The Multiplier using a Multi-precision CSA can solve both problems simultaneously by combining a CSA and a CPA. This paper presents an improved MP-CSA which reduces hardware resources and operation time by changing a MP-CSA's carry chain structure. Consequently, the proposed multiplier is more suitable for the module of long bit multiplication and exponentiation using a modular multiplier repeatedly.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.57-66
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• 2004

This paper proposes the design of a 2,048-bit RSA based on RNS(residue number systems) Montgomery modular multiplier As the systems that RNS processes a fast parallel modular multiplication for a large word partitioned into small words, we introduce Montgomery reduction method(MRM)［1］based on Wallace tree modular multiplier and 33 RNS bases with 64-bit size for RNS Montgomery modular multiplication in this paper. Also, for fast RNS modular multiplication, a modified method based on Chinese remainder theorem(CRT)［2］ is presented. We have verified 2,048-bit RSA based on RNS using Samsung 0.35${\mu}{\textrm}{m}$ technology and the 2,048-bit RSA is performed in 2.54㎳ at 100MHz.

• Journal of the Korea Society of Computer and Information
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• v.6 no.3
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• pp.84-90
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• 2001

The development of network and the other communication-network can generate serious problems. So, it is highly required to control security of network. These problems related secu be developed and keep up to confront with anti-security part such as hacking, cracking. Th way to preserve security from hacker or cracker without developing new cryptographic algori keeping the state of anti-cryptanalysis in a prescribed time by means of extending key-length In this paper, the proposed montgomery multiplication structured unit array method in carry generated part and variable length multiplicator for eliminating bottle neck effect with the RSA cryptosystem. Therefore, this proposed montgomery multiplicator enforce the real time processing and prevent outer cracking.