• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.98-107
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• 2016

An analytical comparison of a synthetic memristor emulator and a M-R mutator-based memristor emulator has been performed. Memristor is an electrical element with the characteristic of variable resistance. It is called the fourth fundamental electrical element following resistor, capacitor, and inductor. Memristor emulator is a circuit which implements the feature of variable resistance via the composition of various electrical devices. It is an essential circuit to study memristor characteristics during the time before it is commercially available. There are two representative memristor emulators depending upon their implementation methods. One is a memristor emulator which is synthesized via combining various electrical devices and the other one is M-R mutator-based memristor emulator implemented by extracting resistance from a nonlinear device. In this paper, implementation methods of these two memristor emulators are studied and their differences are investigated by analysing their characteristics.

• Journal of IKEEE
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• v.17 no.3
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• pp.324-331
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• 2013

In this paper, we implemented memristor emulator circuit on Printed Circuit Board (PCB) and observed the inherent pinched hysteresis characteristic of memristors by measuring the emulator circuit on PCB. The memristor emulator circuit implemented on PCB is composed of simple discrete devices not using any complicated circuit blocks thus we can integrate the memristor emulator circuits in very small layout area on Silicon substrate. The programmable gain amplifier is designed using the proposed memristor emulator circuit and verified that the amplifier's voltage gain can be controlled by programming memristance of the emulator circuit by circuit simulation. Threshold switching is also realized in the proposed emulator circuit thus memristance can remain unchanged when the input voltage applied to the emulator circuit is lower than VREF. The memristor emulator circuit and the programmable gain amplifier using the proposed circuit can be useful in teaching the device operation, functions, characteristics, and applications of memristors to students when thet cannot access to device and fabrication technologies of real memristors.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.65-72
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• 2013

This paper presents design methodology for Memristor-CMOS circuits and its application to primitive IPs design. We proposed a Memristor model and designed basic elements, Memristor AND/OR gates. The primitive IPs based on a Memristor-CMOS technology is proposed for a Memristive system design. The netlists of IPs are extracted from the layouts of Memristor-CMOS and is verified with SPICE-like Memristor model under $0.18{\mu}m$ CMOS technology. As a result, an example design Memristor-CMOS full adder has only 47.6 % of silicon area compare to the CMOS full-adder.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.67-74
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• 2014

This paper presents a memristor-CMOS based RBSD adder. Conventional RBSD adders suffer bigger hardware due to the extra logic handling larger number of bits. The purpose of this paper is to improve the silicon surface area and the computation delay of conventional RBSD adders. The proposed method employs memristor-CMOS based circuit. The implementation results shows that the proposed memristor-CMOS based RBSD adder saves the cell area by 45%, and reduces time delay 24% compared to conventional RBSD adders. The proposed RBSD adder design can bring further area saving for large scale designs.

• Journal of the Korean Institute of Intelligent Systems
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• v.26 no.5
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• pp.368-374
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• 2016

This paper presents an experimental study on an electrical circuit model of the TiO2-based nano-wired memristor device for neuromophic applications. The electrical circuit equivalent model of the proposed memristor device consists of several electronics components and some passive devices including operational amplifiers, multipliers, resistors and capacitors. In order to verify the proposed design, both of simulation (using PSPICE) as well as hardware implementation were performed for the analysis of the memristor circuit with time waveforms, frequency spectra, I-V curves and power curves. The gained results from the measured data showed a good agreement with the simulation result that confirm the proposed idea.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.64-71
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• 2014

Multiplier performs a complex arithmetic operation in various signal processing algorithms such as multimedia and communication system. The multiplier also suffers from its relatively large signal propagation delay, high power dissipation, and large area requirement. This paper presents memristor-CMOS based reconfigurable multiplier reducing area occupation of the multiplier circuitry and increasing compatibility using optimized bit-width for various applications. The performance of the memristor-CMOS based reconfigurable multiplier are estimated with memristor SPICE model and 180 nm CMOS process under 1.8 V supply voltage. The circuit shows performance improvement of 61% for area, 38% for delay and 28% for power consumption respectively compared with the conventional reconfigurable multipliers. It also has an advantage for area reduction of 22% against a twin-precision multiplier.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.49-58
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• 2015

A floating type of memristor emulator which acts like the behavior of $TiO_2$ memristor has been developed. Most of existing memristor emulators are grounded type which is built disregarding the connectivity with other memristor or other devices. The developed memristor emulator is a floating type whose output does not need to be grounded. Therefore, the emulator is able to be connected with other devices and be utilized for the interoperability test with various other circuits. To prove the floating function of the proposed memristor emulator, a Wheatstone bridge is built by connecting 4 memristor emulators in series and parallel. Also this bridge circuit suggest that it is possible to weight calculation of the neural network synapse.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.80-87
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• 2015

Memristor is a new kind of memory device whose resistance varies depending upon applied charge and whose previous resistance state is preserved even when its power is off. Ordinary memristor has a nonlinear programming characteristics about time when a constant voltage is applied. For the easiness of programming, it is desirable that resistance is programmed linearly about time. We had proposed previously a memristor bridge configuration with which weight can be programmed nicely in positive, negative or zero. In memristor bridge circuit, two memristors are connected in series with different polarity. Memristors are complementary each other and it follows that the memristance variation is linear with respect to time. In this paper, the linearization effect of weight programming of memristor bridge synapse is investigated and verified about both $TiO_2$ memristor from HP and a nonlinear memristor with a window function. Memristor bridge circuit would be helpful to conduct synaptic weight programming.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.5
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• pp.1-9
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• 2012

Memristor which is known as fourth basic circuit element has been developed recently but its electrical characteristics are not still fully understood. Memristor has the incremental and decremental feature of the resistance depending upon the connected polarities. Also, its operational behavior become diverse depending on its connection topologies. In this work, electrical characteristics of diverse types of serial and parallel connections are investigated using the HP $TiO_2$ model. The characteristics are analyzed with pinched hystersis loops on the V-I plane when sine input signal is applied. The results of the work would be utilized usefully for analyzing the characteristics of memristor element and applications to logic circuit and neuron cells.

• Electronics and Telecommunications Trends
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• v.29 no.2
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• pp.97-105
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• 2014

본고에서는 시냅스의 생물학적 기능과 이를 모방하는 멤리스터, 멤리스터와 CMOS(Complementary Metal-Oxide-Semiconductor) 트랜지스터의 하이브리드, 그리고 멤리스터 기반의 집적회로 구현에 관한 최신 연구개발 동향을 다루었다. 기억과 스위칭을 동시에 수행할 수 있는 시냅스 모방 멤리스터는 Moore의 법칙에 따른 집적도 한계의 도래시점을 지연시킬 수 있으며, 디지털 컴퓨팅의 한계를 극복하여 학습능력을 가지는 지능형 실시간 병렬처리 시스템을 구현할 수 있는 잠재력을 가지고 있다. 또한 멤리스터는 신경세포의 기능을 재해석하는 계기가 되어 뇌과학 발전에도 크게 기여할 것으로 예상된다. 저전력으로 구동하는 지능형 프로세서의 조기 등장을 위해서는 뇌 과학, 나노소재 및 소자기술, 집적회로 설계 및 공정기술, 뉴로컴퓨팅(neuro-computing) 등 다양한 분야의 융합전략이 요구된다.