• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.39-47
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• 1998

This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.113-120
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• 2007

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. In this paper we proposed reallocation algorithm. All faulty cell of embedded memory is reallocated into the row and column spare memory. This work implements reallocation algorithm and BISR to verify its design.

• Journal of KIISE:Software and Applications
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• v.37 no.10
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• pp.760-767
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• 2010

There are many memory leak detection tools. However, programmers, who develop very large programs, tend to avoid testing their programs with memory leak detection tools since these tools require runtime and space overheads. Thus, we present a memory leak detection technique which enables programmers to test their modules in their unit test phase with low overheads. To achieve this goal, we extend the existing cyclic memory allocation technique and evaluate our memory leak detection technique on a tiny DBMS. In our experiments, we find our tool has reasonably low runtime and space overheads and it reports only a small number of false positives.

• The Journal of the Korea Contents Association
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• v.8 no.4
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• pp.48-54
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• 2008

This paper analyzes cost tradeoffs between memory usage and computation for window-based operators in data stream environments. It identifies generic operator network constructs, and sets up a cost model for the estimation of the expected memory reduction and the computation overheads when window memory relocations are applied to each operator network construct. This cost model helps to identify the utility of window memory relocations. It also helps to apply window memory relocation to improve a query execution plan to save memory usage. The proposed approach contributes to expand the scope of query processing and optimization in data stream environments. It also provides a basis to develop a cost estimation model for the query optimization using window memory relocations.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.34 no.2
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• pp.179-192
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• 2024

macOS presents challenges for memory data acquisition due to its proprietary system architecture, closed-source kernel, and security features such as System Integrity Protection (SIP), which are exclusive to Apple's product line. Consequently, conventional memory acquisition tools are often ineffective or require system rebooting. This paper analyzes the status and limitations of existing memory forensics research and tools related to macOS. We investigate methods for memory acquisition and analysis across various macOS versions. Our findings include the development of a practical memory acquisition and analysis process for digital forensic investigations utilizing OSXPmem and dd tools for memory acquisition without system rebooting, and Volatility 2, 3 for memory data analysis.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.72-82
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• 2014

Recently, the size of semiconductor industry market is constantly growing, due to the increase in diffusion of smart-phone, tablet PC and SSD(Solid State Drive). Also, it is expected that the demand for TLC NAND-type flash memory would gradually increase, with the recent release of TLC NAND-type flash memory in the SSD market. There have been a lot of studies on SLC NAND flash memory, but no research on TLC NAND flash memory has been conducted, yet. Also, a test of NAND-type flash memory is depending on a high-priced external equipment. Therefore, this study aims to suggest a structure for an autonomous test with no high-priced external test device by modifying the existing SLC NAND flash memory and MLC NAND flash memory test algorithms and patterns and applying them to TLC NAND flash memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.30-36
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• 2011

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical bus across memory layers are implemented by many semiconductor companies. 3D memories are composed of known-good-dies (KGDs). If additional faults are arisen during bonding, they should be repaired. In order to enhance the yield of 3D memories with inter-die redundancies, a die-matching method is needed to effectively stack memory dies in a 3D memory. In this paper, a new die-matching method is proposed for 3D memory yield enhancement with inter-die redundancies considering additional faults arisen during bonding. Three boundary-limited conditions are used in the proposed die-matching method; they set bounds to the search spaces for selecting memory dies to manufacture a 3D memory. Simulation results show that the proposed die-matching method can greatly enhance the 3D memory yield.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.4
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• pp.89-100
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• 2011

Physical memory analysis has been an issue on a field of live forensic analysis in digital forensics until now. It is very useful to make the result of analysis more reliable, because record of user behavior and data can be founded on physical memory although process is hided. But most memory analysis focuses on windows based system. Because the diversity of target system to be analyzed rises up, it is very important to analyze physical memory based on other OS, not Windows. Mac OS X, has second market share in Operating System, is operated by loading kernel image to physical memory area. In this paper, We propose a methodology for physical memory analysis on Mac OS X using symbol information in kernel image, and acquire a process information, mounted device information, kernel information, kernel extensions(eg. KEXT) and system call entry for detecting system call hooking. In additional to the methodology, we prove that physical memory analysis is very useful though experimental study.

• Journal of Broadcast Engineering
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• v.27 no.4
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• pp.561-568
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• 2022

Most deep learning-based video object segmentation methods perform the segmentation with past prediction information stored in external memory. In general, the more past information is stored in the memory, the better results can be obtained by accumulating evidence for various changes in the objects of interest. However, all information cannot be stored in the memory due to hardware limitations, resulting in performance degradation. In this paper, we propose a method of storing new information in the external memory without additional memory allocation. Specifically, after calculating the attention score between the existing memory and the information to be newly stored, new information is added to the corresponding memory according to each score. In this way, the method works robustly because the attention mechanism reflects the object changes well without using additional memory. In addition, the update rate is adaptively determined according to the accumulated number of matches in the memory so that the frequently updated samples store more information to maintain reliable information.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.628-630
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• 2004

실시간 운영체제가 탑재되는 임베디드 시스템의 공간제약 특성상 한정된 자원을 가질 수밖에 없기 때문에 자원의 효율적인 사용 및 관리가 필수적이다. 특히 CPU 와 함께 한정된 크기의 메모리는 운영체제의 중요한 자원으로, 효율적인 메모리 관리를 통해 시스템의 성능을 향상시킬 수 있다. 본 논문에서는 실시간 운영체제의 동적 메모리 관리기법 중 메모리 풀에서의 메모리 누수 방지 기법을 설계 및 구현하였다