Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Built-In Redundancy Analysis Algorithm for Embedded Memory Built-In Self Repair with 2-D Redundancy

내장 메모리 자가 복구를 위한 여분의 메모리 분석 알고리즘

  • 심은성 (숭실대학교 컴퓨터학과) ;
  • 장훈 (숭실대학교 컴퓨터학과)
  • Published : 2007.02.25
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Abstract

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. In this paper we proposed reallocation algorithm. All faulty cell of embedded memory is reallocated into the row and column spare memory. This work implements reallocation algorithm and BISR to verify its design.

최근 VLSI 회로 직접도가 급속도로 증가함에 따라 하나의 시스템 칩에 고밀도와 고용량의 내장 메모리가 구현되고 있다. 고장난 메모리를 여분의 메모리로 재배치함으로써 메모리 수율 향상과 사용자에게 메모리를 투명하게 사용할 수 있도록 제공 할 수 있다. 본 논문에서는 고장난 메모리 부분을 여분의 행과 열 메모리 사용으로 고장난 메모리를 고장이 없는 메모리처럼 사용할 수 있도록 여분의 메모리 재배치 알고리즘을 제안하고자 한다.

Keywords

References

  1. Allan A., Edenfeld D., Joyner W.H. Jr., Kahng A.B., Rodgers M., and Zorian, Y., '2001 technology roadmap for semiconductors,' Computer, vol. 35, pp. 42-53, January 2002 https://doi.org/10.1109/2.976918
  2. Jone W.B., Huang D.C., Wu S.C., and Lee K.J., 'An efficient BIST method for distributed small buffers,' IEEE Transactions on Very Large Scale Integration Systems, vol. 10, pp. 512-515, August 2002 https://doi.org/10.1109/TVLSI.2002.800532
  3. Hamdioui S., and van de Goor A.J., 'Thorough testing of any multiport memory with linear tests,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, pp. 217-231, February 2002 https://doi.org/10.1109/43.980260
  4. Hamdioui, S., Gaydadjiev, G., and van de Goor, A.J., 'The state-of-art and future trends in testing embedded memories,' Records of the 2004 International Workshop, Memory Technology, Design and Testing, pp. 54-59, 9-10 August 2004 https://doi.org/10.1109/MTDT.2004.1327984
  5. Horiguchi M., Etoh J., Aoki M., Itoh K., and Matsumoto T., 'A flexible redundancy technique for high-density DRAMs,' IEEE Journal of Solid-State Circuits, vol. 26, pp. 12-17, January 1991 https://doi.org/10.1109/4.65704
  6. Ilyoung Kim, Zorian Y., Komoriya G., Pham H., Higgins F.P., and Lewandowski J.L., 'Built in self repair for embedded high density SRAM,' Proceedings of International Test Conference, pp. 1112-1119, 18-23 October 1998 https://doi.org/10.1109/TEST.1998.743312
  7. Heon Cheol Kim, Dong Soon Yi, Jin Young Park, and Chang Hyun Cho, 'A BISR (built-in self-repair) circuit for embedded memory with multiple redundancies,' International Conference on VLSI and CAD, pp. 602-605, 26-27 October 1999 https://doi.org/10.1109/ICVC.1999.821012
  8. Sy Yen Kuo, and Fuchs W.K., 'Efficient Spare Allocation in Reconfigurable Arrays' Conference on Design Automation, pp. 385-390, 29-2 June 1986
  9. Chin Long Wey, and Lombardi F., 'On the Repair of Redundant RAM's,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 6, pp. 222-231, March 1987 https://doi.org/10.1109/TCAD.1987.1270266
  10. Wei Kang Huang, Yi Nan Shen, and Lombardi F., 'New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, pp. 323-328, March 1990 https://doi.org/10.1109/43.46807
  11. Schober V., Paul S., and Picot O., 'Memory built-in self-repair using redundant words,' Proceedings of International Test Conference, pp. 995-1001, 30 October-1 November 2001 https://doi.org/10.1109/TEST.2001.966724
  12. Shyue Kung Lu, Yu Chen Tsai, Hsu C. H., Kuo Hua Wang, and Cheng Wen Wu, 'Efficient built-in redundancy analysis for embedded memories with 2-D redundancy,' IEEE Transactions on Very Large Scale Integration Systems, vol. 14, pp. 34-42, January 2006 https://doi.org/10.1109/TVLSI.2005.863189