• Journal of KIISE:Software and Applications
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• v.34 no.5
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• pp.487-501
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• 2007

To achieve high resource utilization for multi-issue DSPs, production compiler commonly includes variants of iterative modulo scheduling algorithm. However, excessive cyclic data dependences, which exist in communication and media processing loops, unduly restrict modulo scheduling freedom. As a result, replicated functional units in multi-issue DSPs are often under-utilized. To address this resource under-utilization problem, our paper describes a novel compiler preprocessing strategy for effective modulo scheduling. The preprocessing strategy proposed capitalizes on two new transformations, which are referred to as cloning and dismantling. Our preprocessing strategy has been validated by an implementation for StarCore SC140 DSP compiler.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.182-185
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• 2019

This paper analyzes performances of modules in implementing a programmable multi-format video decoder. The goal of the proposed platform is the high-end Full High Definition (FHD) video decoder. The proposed multi-format video decoder consists of a reconfigurable processor, dedicated bit-stream co-processor, memory controller, cache for motion compensation, and flexible hardware accelerators. The experiments suggest performance baseline of modules for the proposed architecture operating at 300 MHz clock with capability of decoding HEVC bit-streams of FHD 30 frames per second.

• The Journal of Korean Association of Computer Education
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• v.8 no.4
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• pp.87-95
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• 2005

A large part of the wireless Internet contents which the young people access through their mobile phones is mobile games. However, mobile games currently available in the market are mostly simple entertainment packages, and there are hardly any educational game contents. This research divided the middle school computer education curriculum into five parts-common PC knowledge, operating systems, word processor, Internet, and multimedia-and designed and implemented a crossword puzzles mobile game. The mobile game designed in this research was given an emphasis to allow access of school lesson contents anywhere and anytime through actual mobile telecommunication networks, so that the students may experience less barrier to more fun and entertaining educational contents. The developed educational mobile game was applied on 2nd year middle school students. The mobile game had positive educational effects.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12B
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• pp.831-837
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• 2005

Personal general purpose computer(PC) has been evolved from desktop to portable mobile device such as tablet PC and PDA. Technology innovation on semiconductor have made it possible to package a reasonably Powerful Processor and memory subsystem with advanced input/output devices. At last these subsystems are miniaturized into wearable system. Wearable computer has recently gained attention as the post PC in the ubiquitous environment. Wearable computing becomes more and more feasible and receives growing attention throughout industry and the consumer marketplaces. This paper proposed and developed WPS that has multimedia features and network features as a wearable embedded platform. We explain the form, overall architecture, functions and user applications of this WPS. This paper also discusses the form of next generation computer platform with intuitive user interfaces and well designed applications in the future.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.5
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• pp.477-485
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• 2002

In this paper, we present an efficient hardware architecture for the H.263 video codec and its VLSI implementation. This architecture is based on the unified interface by which internal hardware engines and an internal RISC processor are connected one another. The unified interface enables the modular design of internal blocks, efficient hardware/software partitioning, and pipelined paralled operations. The developed VLSI supports the H.263 version 2 profile 3 @ level 10, and moreover, both the control protocol H.245 and the multiplexing protocol H.223. Therefore, it can be used for the complete ITU-T H.324 or 3GPP 3G 324M multimedia processor with the help of an external audio codec. Simultaneous encoding and decoding of QCIF format images at a rate greater than 15 frames per second is achieved at 40 MHz clock frequency.

• Journal of KIISE:Information Networking
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• v.36 no.5
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• pp.376-382
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• 2009

The recent growth of cable broadcast technology such as Tru2Way enables the cable service operator to provide more enhanced experiences to cable TV audience. As a result, various applications have been produced and user can easily access cable network to receive multimedia content as well as interactive application in cable environment. In order for current cable technology to be accepted as a web extended technology, a process of web based applications having a web document and multimedia resources, proper web service definition and middleware architecture for existing cable environment should be established. In this paper, we define a web application for cable environment and propose a middIeware architecture which can process web application based on Tru2Way technology

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.631-634
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• 2009

Recent advances in wireless communication, electronics, MEMS device, sensor and battery technology have made it possible to manufacture low-cost, low-power, multi-function tiny sensor nodes. A large number of tiny sensor nodes form sensor network through wireless communication. Sensor networks represent a significant improvement over traditional sensors, research on Zigbee wireless image transmission has been a topic in industrial and scientific fields. In this paper, we design a Zigbee wireless image sensor node and multimedia monitoring server system. It consists of embedded processor, memory, CMOS image sensor, image acquisition and processing unit, Zigbee RF module, power supply unit and remote monitoring server system. In the future, we will further improve our Zigbee wireless image sensor node and monitoring server system. Besides, energy-efficient Zigbee wireless image transmission protocol and interworking with mobile network will be our work focus.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.7-16
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• 2007

In this paper, we introduce a new design environment for efficient multiprocessor system-on-chip design space exploration. The design environment takes a process network model as input system specification. The process network model has been widely used for modeling signal processing applications because of its excellent modeling power. However, it has limitation in predictability, which could cause severe problem for real time systems. This paper proposes a new approach that enables static analysis of a process network model by converting it to a hierarchical synchronous dataflow model. For efficient design space exploration in the early design step, mapping application to target architectures has been a crucial part for finding better solution. In this paper, we propose an efficient mapping algorithm. Our mapping algorithm supports both single bus architecture and multiple bus architecture. In the experiments, we show that the automatic conversion approach of the process network model for static analysis is performed successfully for several signal processing applications, and show the effectiveness of our mapping algorithm by comparing it with previous approaches.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1218-1226
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• 2008

With the development of semiconductor integrated technology and with the increasing use of multimedia functions in computer, more functions have been implemented as hardware. Nowadays, most microprocessors beyond 32 bits generally implement an integer multiplier as hardware. However, as for a divider, only specific microprocessor implements traditional SRT algorithm as hardware due to complexity of implementation and slow speed. This paper suggested an algorithm that uses a multiplier, 'w bit $\times$ w bit = 2w bit', to process $\frac{N}{D}$ integer division. That is, the reciprocal number D is first calculated, and then multiply dividend N to process integer division. In this paper, when the divisor D is '$D=0.d{\times}2^L$, 0.5 < 0.d < 1.0', approximate value of ' $\frac{1}{D}$', '$1.g{\times}2^{-L}$', which satisfies ' $0.d{\times}1.g=1+e$, $e<2^{-w}$', is defined as over reciprocal number and then an algorithm for over reciprocal number is suggested. This algorithm multiplies over reciprocal number '$01.g{\times}2^{-L}$' by dividend N to process $\frac{N}{D}$ integer division. The algorithm suggested in this paper doesn't require additional revision, because it can calculate correct reciprocal number. In addition, this algorithm uses only multiplier, so additional hardware for division is not required to implement microprocessor. Also, it shows faster speed than the conventional SRT algorithm and performs operation by word unit, accordingly it is more suitable to make compiler than the existing division algorithm. In conclusion, results from this study could be used widely for implementation SOC(System on Chip) and etc. which has been restricted to microprocessor and size of the hardware.