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http://dx.doi.org/10.5909/JBE.2019.24.1.182

Analysis of Components Performance for Programmable Video Decoder  

Kim, Jaehyun (Seoul National University of Science and Technology, Graduate School of NID Fusion Technology)
Park, Gooman (Seoul National University of Science and Technology, Graduate School of NID Fusion Technology)
Publication Information
Journal of Broadcast Engineering / v.24, no.1, 2019 , pp. 182-185 More about this Journal
Abstract
This paper analyzes performances of modules in implementing a programmable multi-format video decoder. The goal of the proposed platform is the high-end Full High Definition (FHD) video decoder. The proposed multi-format video decoder consists of a reconfigurable processor, dedicated bit-stream co-processor, memory controller, cache for motion compensation, and flexible hardware accelerators. The experiments suggest performance baseline of modules for the proposed architecture operating at 300 MHz clock with capability of decoding HEVC bit-streams of FHD 30 frames per second.
Keywords
Cache; Coarse grain array; HEVC; Multi-format video decoder; Reconfigurable processor;
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