• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.65-70
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• 2008

A novel fast locking dual-loop integer-N phase locked loop(PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a $0.35{\mu}m$ CMOS process with a 3.3V supply voltage. Simulation results show the fast look time of $50{\mu}s$ for an 80MHz frequency jump in a 200KHz channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.899-905
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• 2017

This paper presents a reference-less dual loop clock and data recovery (CDR) circuit that supports a data rate of 2.496 Gb/s for the mobile industry processor interface (MIPI) M-PHY. An adaptive loop bandwidth scheme is used to implement the fast lock time maintaining a low time jitter. To this scheme, the proposed CDR consists of two loops for a frequency locked loop and a phase locked loop. The proposed 2.496 Gb/s reference-less dual loop CDR is designed using a 65 nm CMOS process with 1.2 V supply voltage. The simulated peak-to-peak jitter of output clock is 9.26 ps for the input data of 2.496 Gb/s pseudo-random binary sequence (PRBS) 15. The active area and power consumption of the implemented CDR are $470{\times}400{\mu}m^2$ and 6.49 mW, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1117-1122
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• 2005

This paper is studied the high-repetition rate optical-pulse stream generation using optical loop mirror coupler. With the recent development of the ultrahigh-speed optical time division multiplexed system, hish-repetition rate optical-pulse stream generation is necessary. This is different from conventional approaches, which use fiber or integrated waveguide delay line circuits. The high-repetition-rate optical-pulse multiplication phenomenon occurs when the optical pulse's spectral width is greater than the transfer bandwidth of the coupler used. From the analysis, the output repetition rate can be controlled by using fiber couplers with different equivalent transfer bandwidths. The pulse separation spacing is controlled by number of cascaded coupler in optical loop mirror coupler scheme.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.531-537
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• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.651-657
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• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.90-96
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• 2014

This paper presents a practical linearization technique for a wide-band bang-bang digital phase locked-loop(BBDPLL) by selecting optimal loop gains. In this paper, limitation of the theoretical design method for BBDPLL is explained, and introduced how to implement practical BBDPLLs with CMOS process. In the proposed BBDPLL, the limited cycle noise is removed by reducing the proportional gain while increasing the integer array and dither gain. Comparing to the conventional BBDPLL, the proposed one shows a small area, low power, linear characteristic. Moreover, the proposed design technique can control a loop bandwidth of the BBDPLL. Performance of the proposed BBDPLL is verified using CppSim simulator.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.12
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• pp.171-176
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• 2005

This study designed and fabricated a multi-purpose planar antenna for base stations that are accessible to DCS, WiBro, and ISM. The proposed antenna was designed into an open loop form from the existing monopole structure. The capacitance of the multi-purpose antenna was increased by the coupling of open parts. This makes the use of MMIC and LTCC convenient and the antenna is smaller and has a larger gain than existing antennas. The resonance distance and bandwidth can be adjusted by changing the open gap and the height of the loop of the antenna. The bandwidth of the designed antenna satisfies DCS, IMT-2000, WiBro, Bluetooth, wireless LAN and ISM bands based on VSWR 2. The entire frequency bandwidth is $58.75\%$ of $1.575GHz\~2.985GHz(1.41GHz)$. Also, the radiation pattern of the antenna displayed co-polarization and cross-polarization characteristics at 1.6GHz, 2.3GHz and 2.8GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.10
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• pp.1021-1030
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• 2009

We propose optimization method of two-inductor loaded small loop antennas using simple genetic algorithm. To optimize the loop antennas for the RFID and the mobile phone band, we changed positions and values of the two inductors in the loop antenna. Visual basic was used to make genetic algorithm and to calculate fitness values by controlling the commercial EM software. The bandwidth of the optimized RFID loop antenna is 10 MHz at the center frequency of 922 MHz and that of the mobile phone antenna are 84 MHz and 266 MHz at the center frequency of 948 MHz(GSM band) and 1.81 GHz(DCS band), respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.599-607
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• 2004

In this paper, using phase locked loop(PLL) synthesizer, we introduce a novel but simple and low cost frequency modulation(FM) circuit of a flat peak frequency deviation fur modulation signal whose frequency covers from outside to inside of the loop-bandwidth of PLL. The FM circuit was basically designed to compensate an amount of feedback of the loop filter in PLL. The circuit also includes the capability of the adjustment of peak frequency deviation and of blocking the intereference with the loop filter. The designed circuit was successfully implemented and showed the flat frequency deviation as expected in the design. In addition, the novel measurement method of the wideband FM modulation index is suggested verified With the suggest measurement, it can be successfully shown the designed circuit has the expected frequency deviation.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.12a
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• pp.205-208
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• 2000

In this paper, we'll show that an improved PDFF controller is obtained by substituting a feedforward compensator in the existing PDFF system with a dual-input describing function, and the controller has the ability of adjusting the bandwidth of a system as well as the phase margin simultaneously. The effectiveness of the proposed controller is confirmed by applying to the DC-motor position control system. As the results of simulation, we know that it is possible to design a controller by which the bandwidth of the closed system and its phase margin are easily adjusted.