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http://dx.doi.org/10.17661/jkiiect.2018.11.6.651

Spur Reduced PLL with ΔΣ Modulator and Spur Reduction Circuit  

Choi, Young-Shig (Department of Electronic Engineering, Pukyong National University)
Han, Geun-Hyeong (Department of Electronic Engineering, Pukyong National University)
Publication Information
The Journal of Korea Institute of Information, Electronics, and Communication Technology / v.11, no.6, 2018 , pp. 651-657 More about this Journal
Abstract
A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.
Keywords
PLL; Loop Filter; Spur; Delta-sigma modulator; Spur reduction circuit;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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